LFSR, PRBS & CRC

8-Bit Galois LFSR (x⁸+x⁶+x⁵+x⁴+1)

8-bit Galois LFSR with parallel load/shift enables using polynomial x^8+x^6+x^5+x^4+1.

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About this block

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8-Bit Galois LFSR (x⁸+x⁶+x⁵+x⁴+1) is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit Galois Linear Feedback Shift Register (LFSR) with parallel load capability. It is designed for FPGA and ASIC synthesis, offering a robust pseudo-random number generator core with flexible initialization via parallel load. The design is fully verified using Icarus Verilog and supports synchronous reset and independent control signals for load and shift operations.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Galois LFSR (x⁸+x⁶+x⁵+x⁴+1).
Read the Verilog module in the editor. The catalog line for this block: 8-bit Galois LFSR with parallel load/shift enables using polynomial x^8+x^6+x^5+x^4+1.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit State Width: Standard width for byte-aligned operations.
Galois Configuration: Efficient hardware implementation with low logic depth using polynomial x^8 + x^6 + x^5 + x^4 + 1.
Parallel Load: Arbitrary state initialization via parallel_in input.
Synchronous Control: Independent load_en and shift_en signals with defined priority (Reset > Load > Shift).
Synchronous Reset: Reset to zero via rst_n on the positive clock edge.
High Frequency: Optimized feedback logic for high-speed operation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`load_en`	Input	1	Parallel load enable (high priority)
`shift_en`	Input	1	Shift enable (low priority)
`parallel_in`	Input	8	Parallel data input
`state`	Output	8	Current LFSR state

Verification

The testbench (tb/tb_lfsr_8bit_galois.v) verifies the following behaviors:

Reset Behavior: Ensures state is zero after reset.
Parallel Loading: Validates loading arbitrary values (0xAA, 0xFF).
Shift Sequence: Confirms correct Galois LFSR progression from 0x01 to 0x71.
Hold State: Ensures state remains unchanged when no enables are active.

All test cases passed successfully.

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