LFSR, PRBS & CRC

8-Bit Fibonacci LFSR (Right-Shift + Mask XOR) — L1 Upgrade

An 8-bit Fibonacci Linear Feedback Shift Register supporting right-shift, mask XOR feedback, load, and arithmetic increment modes.

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8-Bit Fibonacci LFSR (Right-Shift + Mask XOR) — L1 Upgrade is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit Fibonacci Linear Feedback Shift Register (LFSR) with right-shift behavior. It supports three operational modes:

LFSR Mode: Generates pseudo-random sequences using taps at bits [7], [5], and [4].
Load Mode: Loads data_in directly into the state register.
Arithmetic Mode: Increments the current state by 1.

The design is targeted at beginner-level integration (Difficulty Level 1) and is fully verified with a testbench using Icarus Verilog.

The module generates pseudo-random sequences using a Fibonacci tap configuration.

Polynomial: $x^8 + x^6 + x^5 + x^4 + 1$
Taps: Bits [7], [5], and [4] are XORed to form the new MSB.
Operation: Right-shift operation moves data toward lower indices.
Reset Value: The state is initialized to 8'b1 on asynchronous reset.

LFSR Mode: Standard feedback shift. The new MSB is calculated as state[7] ^ state[5] ^ state[4].
Load Mode: Loads data_in into the state register. This mode has the highest priority.
Arithmetic Mode: Increments the state by 1. This mode is active when arithmetic_mode is high and load is low.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Fibonacci LFSR (Right-Shift + Mask XOR) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit Fibonacci Linear Feedback Shift Register supporting right-shift, mask XOR feedback, load, and arithmetic increment modes.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The core state machine updates on the positive clock edge. Reset initializes the state to 8'b1. Three modes are controlled by valid, load, and arithmetic_mode signals.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock signal
rst_n	Input	1	Active-low asynchronous reset
load	Input	1	Load `data_in` into state (Priority: High)
valid	Input	1	Enable state update
arithmetic_mode	Input	1	Select increment mode over LFSR (Priority: Medium)
data_in	Input	8	Input data for load or arithmetic
data_out	Output	8	Current state value
busy	Output	1	High when `valid` is asserted

Verification

The testbench validates reset, load, LFSR stepping, arithmetic mode, and busy signaling. Simulation uses Icarus Verilog and generates a VCD dump.

Test Case	Description	Expected Result	Status
TC1	Reset Check	State equals `8'b1`	PASS
TC2	Load Check	State equals `8'b10101010`	PASS
TC3	LFSR Step	State equals `8'b01010101`	PASS
TC4	Arithmetic Step	State equals `8'b00000010`	PASS
TC5	Busy Signal	Busy equals `1'b1`	PASS
TC6	Valid Low	State remains unchanged	PASS

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