LFSR, PRBS & CRC

Trivium-Lite Keystream 8-bit

A simplified Trivium-Lite NFSR generating 8-bit keystream from an 80-bit state.

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About this block

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Trivium-Lite Keystream 8-bit is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A lightweight, synthesizable Verilog implementation of a simplified Trivium-Lite Non-Linear Feedback Shift Register (NFSR). Designed for resource-constrained environments and educational purposes, this module generates an 8-bit keystream from an 80-bit internal state.

This repository provides a fully verified Verilog module (trivium_lite_keystream_8) that implements an 80-bit NFSR.

It supports synchronous Key/IV initialization via an 8-bit input and features an active-low asynchronous reset.

Choose Open in IDE. RTL Studio loads the packaged workspace for Trivium-Lite Keystream 8-bit.
Read the Verilog module in the editor. The catalog line for this block: A simplified Trivium-Lite NFSR generating 8-bit keystream from an 80-bit state.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Compact State: 80-bit NFSR state register.
Output: 8-bit keystream generated via specific XOR taps from the upper state bits.
Initialization: Synchronous load for Key/IV; supports zero-initialization of upper bits.
Reset: Active-low asynchronous reset.
Verification: Fully verified with Icarus Verilog simulation suite.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low asynchronous reset
`key_iv`	Input	8	Key/IV data to load into state
`load`	Input	1	Active-high load enable
`keystream`	Output	8	Generated keystream bits

Architecture

The module implements a single 80-bit shift register. The feedback logic computes a new bit by XORing specific taps from the state register:

Feedback Taps: Indices 66, 61, 55, 22, and 0.
Output Logic: The 8-bit keystream is derived by XORing four specific bits from the upper portion of the state register. Each output bit shifts its source indices downwards.

Verification

The provided testbench (tb_trivium_lite_keystream_8.v) validates the following scenarios:

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Load Key/IV Timing	PASS
TC3	Keystream Dynamics	PASS
TC4	Known Vector Simulation	PASS

### Running Simulation

To run the simulation, ensure you have Icarus Verilog installed.

Expected Output:

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