RTL Studio Open IDE

LFSR, PRBS & CRC

16-Bit Fibonacci LFSR (Left-Shift, Fixed Taps) — L1 Upgrade — L2 Upgrade

16-bit Fibonacci Linear Feedback Shift Register with left-shift architecture, fixed taps (x^16+x^15+x^13+x^4+1), and zero-state lock detection.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

16-Bit Fibonacci LFSR (Left-Shift, Fixed Taps) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a 16-bit Fibonacci Linear Feedback Shift Register (LFSR) using a left-shift architecture with fixed taps.

It is designed for pseudo-random number generation (PRNG), built-in self-test (BIST), and scrambling applications.

The core generates a maximal-length sequence of $2^{16}-1$ states for any non-zero seed and includes a built-in zero-state detection mechanism (lock signal) to handle the illegal all-zero state.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Fibonacci LFSR (Left-Shift, Fixed Taps) — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 16-bit Fibonacci Linear Feedback Shift Register with left-shift architecture, fixed taps (x^16+x^15+x^13+x^4+1), and zero-state lock detection.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Architecture: Left-shift Fibonacci LFSR.
  • Polynomial: $x^{16} + x^{15} + x^{13} + x^4 + 1$ (Primitive).
  • Taps: Bits 15, 13, and 4 (MSB to LSB indexing).
  • Zero-State Detection: The lock output asserts high when the LFSR state becomes all zeros. This serves as an error indicator or stall enable for external logic.
  • Maximal Length: Generates a sequence of length $2^{16}-1$ for any non-zero seed.
  • Synchronous Control: Supports synchronous reset and load operations.

Architecture

The LFSR shifts data to the left on every rising clock edge. Feedback is calculated by XORing the output bits at the tap positions (15, 13, and 4). The resulting feedback bit is inserted into the least significant bit (LSB) position.

A dedicated detection mechanism monitors the internal state. If the state becomes all zeros (an illegal state for maximal-length LFSRs), the lock output asserts high. External logic can use this signal to halt further processing or reload a seed.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
loadInput1Load enable. When high, seed is loaded into q
seedInput16Seed value for initialization
lockOutput1Asserted high when LFSR state is zero
qOutput16Current LFSR state

Verification

The IP includes a comprehensive testbench (tb_lfsr_16bit_fibonacci_lshift_fixed_taps_arithmetic_mode_seed_lock.v) that verifies:

  1. Reset Behavior: Ensures q and lock are cleared on reset.
  2. Load Functionality: Verifies that the seed is correctly loaded into q.
  3. Shift Logic: Confirms correct left-shift behavior with fixed taps.
  4. Lock Detection: Validates that lock asserts when the state is zero.
  5. Long-Run Stability: Runs 100+ cycles with non-zero seeds to ensure no false lock assertions.

All test cases pass successfully, confirming maximal-length sequence generation for non-zero seeds.

More in LFSR, PRBS & CRC

All LFSR, PRBS & CRC blocks