LFSR, PRBS & CRC

Xorshift64* PRNG

64-bit Xorshift pseudo-random number generator with seed loading and enable control.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Xorshift64* PRNG is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a Xorshift64* pseudo-random number generator (PRNG).

It generates a 64-bit random sequence using linear feedback shift registers.

The design supports configurable seeding, clock enable gating for power savings, and asynchronous reset.

Choose Open in IDE. RTL Studio loads the packaged workspace for Xorshift64* PRNG.
Read the Verilog module in the editor. The catalog line for this block: 64-bit Xorshift pseudo-random number generator with seed loading and enable control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

64-bit State Width: Provides a long period and high-quality randomness.
Configurable Seed: Load any 64-bit seed via the load_seed interface.
Clock Enable: Supports en signal to gate state updates for power saving.
Asynchronous Reset: Resets to a fixed initial state (1) on rst_n assertion.
Synchronous Output: Output is valid on every clock cycle when enabled.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Clock enable signal
`load_seed`	Input	1	Load seed control signal
`seed_in`	Input	64	Seed data input
`rand_out`	Output	64	Random number output

Architecture

The core algorithm updates the state using XOR and shift operations. The specific sequence of operations for Xorshift64* is:

s1 = state ^ (state >> 12)
s2 = s1 << 25
s3 = s2 >> 18
next_state = state ^ s1 ^ s2 ^ s3

Verification

The provided testbench (tb_xorshift64_star) validates the following behaviors:

TC1: Reset behavior (initial state is 1).
TC2: Seed loading functionality.
TC3: Output stability when en is low.
TC4: Output changes when en is high.
TC5: Sequence validity (non-zero, distinct values).

### Running Simulation

To run the simulation and verify the results:

Expected Output:

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