LFSR, PRBS & CRC

32-Bit Fibonacci LFSR (Right-Shift + Enable) — L2 Upgrade

A 32-bit Fibonacci Linear Feedback Shift Register with right-shift architecture, enable control, and golden-value lock detection.

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32-Bit Fibonacci LFSR (Right-Shift + Enable) — L2 Upgrade is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 32-bit Fibonacci Linear Feedback Shift Register (LFSR). It uses a right-shift architecture with enable control and lock detection. The design targets Level 2 complexity for educational and verification purposes.

This IP provides a robust 32-bit LFSR with lock detection capabilities.

It is suitable for test pattern generation and state machine sequencing.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Fibonacci LFSR (Right-Shift + Enable) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 32-bit Fibonacci Linear Feedback Shift Register with right-shift architecture, enable control, and golden-value lock detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

32-bit Fibonacci LFSR: Generates pseudo-random sequences using a standard primitive polynomial.
Right-Shift Architecture: Feedback is injected into the MSB after shifting right.
Enable Control: Synchronous state updates gated by an en signal.
Lock Detection: Compares the current state against a golden seed value and asserts a flag on match.
Synchronous Reset: Active-low reset initializes the LFSR to a specific seed.

Architecture

The LFSR uses taps at positions 0, 10, 30, and 31 (0-indexed). Feedback is computed using XOR operations on these tap bits. The shift direction is right, with feedback injected into the MSB (bit 31).

Lock detection compares the current output register lfsr_out with the golden input. The lock_flag asserts high when they match.

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low synchronous reset
`en`	Input	1	Enable signal for shifting
`golden`	Input	32	Reference value for lock detection
`lfsr_out`	Output	32	Current LFSR state
`lock_flag`	Output	1	Asserted when `lfsr_out` equals `golden`

Verification

The testbench verifies reset behavior, shifting, and lock detection. It confirms the initial seed value upon reset. It checks the first shift cycle for correct feedback calculation. It validates that the lock flag asserts when the golden value matches. It ensures the lock flag clears when the golden value changes. It verifies that the state holds when the enable signal is deasserted.

Test Case	Description	Result
TC1	Reset value and lock flag initialization	PASS
TC2	First shift cycle and feedback logic	PASS
TC3	Lock detection assertion on match	PASS
TC4	Lock detection clearance on mismatch	PASS
TC5	State hold on disable	PASS

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