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LFSR, PRBS & CRC

64-Bit LFSR (2 Tap-Set Parameter Select)

64-bit LFSR with parameter TAP_SEL choosing between two fixed tap sets, plus load and enable.

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About this block

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64-Bit LFSR (2 Tap-Set Parameter Select) is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 64-bit Linear Feedback Shift Register (LFSR) with maximal-length sequence generation. It supports two configurable primitive polynomials via a parameter select signal. The design includes parallel load, synchronous reset, and enable gating capabilities.

This IP provides a robust 64-bit LFSR with flexible tap configuration. It is suitable for applications requiring pseudo-random number generation or testing. The design is fully verified for reset, load, and enable functionalities. Simulation results confirm correct operation for both tap sets.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 64-Bit LFSR (2 Tap-Set Parameter Select).
  2. Read the Verilog module in the editor. The catalog line for this block: 64-bit LFSR with parameter TAP_SEL choosing between two fixed tap sets, plus load and enable.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 64-bit state width for long pseudo-random sequences.
  • Configurable tap sets via the TAP_SEL parameter.
  • Synchronous reset to zero state.
  • Parallel load capability for seeding the LFSR.
  • Enable gating to hold state during idle periods.
  • Maximal-length sequence generation (excluding all-zero state).

Ports

Port NameDirectionWidthDescription
clkInput1Clock input for synchronous operations.
rst_nInput1Active-low synchronous reset signal.
enInput1Enable signal to advance the LFSR state.
seedInput64Parallel load data for the LFSR state.
loadInput1Active-high signal to load seed into the LFSR.
qOutput64Current state of the LFSR.

Architecture

The core state register lfsr_reg updates on the positive edge of clk. Reset forces the register to zero when rst_n is low. Load overrides the shift operation when load is high, capturing seed. Enable gating prevents state updates when en is low. Feedback logic computes the XOR of specific taps based on TAP_SEL. Tap Set 0 uses taps at indices 0, 1, 2, and 3. Tap Set 1 uses taps at indices 0, 1, 5, and 6. The feedback bit is inserted at the MSB (bit 63) during right shifts.

Verification

The testbench verifies reset, load, enable gating, and sequence logic.

Test CaseDescriptionExpected Result
TC1Reset TestOutput q becomes 64'h0 when rst_n is low.
TC2Load Seed TestOutput q matches seed when load is high.
TC3Enable Gating TestOutput q remains constant when en is low.
TC4Sequence Logic TestOutput q changes every cycle and never hits 0 for 100 cycles.
TC5Different Seed Load TestOutput q matches 64'hFFFFFFFFFFFFFFFF when loaded.

All tests passed successfully in the simulation log. The simulation confirms correct maximal-length sequence behavior for the selected taps.

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