RTL Studio Open IDE

LFSR, PRBS & CRC

PRBS-32 Sequence Generator

A 32-bit Pseudo-Random Binary Sequence generator using the IEEE 802.3 polynomial. Supports synchronous reset, enable control, and seed reload for deterministic testing.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumsystemverilogsimsyn

PRBS-32 Sequence Generator is a SystemVerilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 32-bit Pseudo-Random Binary Sequence (PRBS) generator based on the IEEE 802.3 standard polynomial. It is designed for high-speed data integrity testing, offering synchronous reset, enable control, and deterministic seed reload capabilities. The module is fully synthesizable, latch-free, and provides a simple interface for integration into verification environments or hardware stress tests.

The core of this IP is a Linear Feedback Shift Register (LFSR) with 32 bits of state. It uses the primitive polynomial:

x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for PRBS-32 Sequence Generator.
  2. Read the SystemVerilog module in the editor. The catalog line for this block: A 32-bit Pseudo-Random Binary Sequence generator using the IEEE 802.3 polynomial. Supports synchronous reset, enable control, and seed reload for deterministic testing.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Standard Compliance: Uses the IEEE 802.3 PRBS-32 polynomial.
  • Synchronous Control: Supports active-low synchronous reset and enable signals.
  • Deterministic Testing: Allows loading a specific seed to reproduce sequences.
  • Parallel Output: Exposes the full 32-bit LFSR state for monitoring.
  • Synthesizable: Fully synthesizable RTL with no latches.

Interface

Signal NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
enInput1Enable signal to advance state
load_seedInput1Load seed_d into state register
seed_dInput32Data to load into state register
prbs_outOutput32Current LFSR state

Architecture

The LFSR updates its state on the positive edge of the clock. The next state is determined by:

  1. Reset: If rst_n is low, the state is cleared to zero.
  2. Seed Load: If load_seed is high, the state is loaded with seed_d.
  3. Shift: If en is high, the state shifts right, and the new MSB is the XOR of specific tap bits (feedback).
  4. Hold: If neither reset nor seed load is active and en is low, the state remains unchanged.

### Feedback Logic

The feedback bit is calculated by XORing the bits at positions defined by the polynomial taps:

Verification

The provided testbench (tb_prbs_32b.sv) includes seven test cases to ensure correctness:

  1. Reset Verification: Confirms output is zero after reset.
  2. Seed Load Verification: Confirms output matches the loaded seed.
  3. Enable/Shift Verification: Confirms state changes when enabled.
  4. Determinism Verification: Confirms reloading the seed produces the same sequence.
  5. Edge Cases: Tests all-zeros and all-ones seeds.
  6. Statistical Properties: Verifies ~50% Hamming weight over long sequences.

All tests pass successfully in simulation.

More in LFSR, PRBS & CRC

All LFSR, PRBS & CRC blocks