LFSR, PRBS & CRC

8-Bit Parallel Scrambler — L2 Upgrade

8-bit parallel scrambler with LFSR state, shadow register, invalidate, and byte-enable features.

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8-Bit Parallel Scrambler — L2 Upgrade is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit parallel scrambler using a Linear Feedback Shift Register (LFSR) with polynomial x^8 + x^6 + x^5 + x^4 + 1 (Hex: 0x5B). It is designed for applications requiring data whitening with robust state management, including non-destructive state preservation via a shadow register and immediate reset control via an invalidate mechanism.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Parallel Scrambler — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit parallel scrambler with LFSR state, shadow register, invalidate, and byte-enable features.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Parallel Data Path: Supports full byte processing with XOR scrambling.
LFSR Polynomial: x^8 + x^6 + x^5 + x^4 + 1 (Hex: 0x5B).
Shadow Register: Allows non-destructive state updates via commit_shadow.
Immediate Invalidate: invalidate signal clears state, shadow, and busy flags immediately.
Handshaking: busy flag indicates active processing; valid_in/valid_out strobes.
Synchronous Reset: Controlled via active-low rst_n.

Architecture

The module consists of a combinational scrambler and a sequential LFSR state machine.

Output Logic: data_out is the registered XOR of data_in and the current LFSR state.
LFSR Logic: Shifts right; feedback is the LSB XORed with the polynomial.
State Management:

- shadow_reg holds a backup of the state. - commit_shadow loads shadow_reg into state. - invalidate forces all state registers to zero.

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`data_in`	Input	8	Data to be scrambled
`valid_in`	Input	1	Input data valid strobe
`byte_en`	Input	1	Byte enable for shadow update (logic-dependent)
`invalidate`	Input	1	Force clear state/shadow/busy
`commit_shadow`	Input	1	Load shadow register into LFSR state
`data_out`	Output	8	Scrambled data output
`valid_out`	Output	1	Output data valid strobe
`busy`	Output	1	Busy indicator during processing

Verification

The testbench tb_scrambler_invalidate_shadow_8b.v covers the following scenarios:

Test Case	Description	Expected Result
TC1	Basic Scramble	Output matches input XOR state (e.g., `0x12 ^ 0x00 = 0x12`)
TC2	Invalidate	Busy clears, state resets to 0
TC3	Shadow Commit	State updates from shadow, `valid_out` remains high
TC4	Byte Enable	Busy flag asserts correctly with `byte_en`
TC5	Busy Flag	Busy asserts during `valid_in` and deasserts after

All tests passed in simulation logs.

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