About this block
Simulate it in the Verilog IDE
CRC-16-CCITT Serial is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP implements a serial CRC-16-CCITT (CRC-16/CCITT-FALSE) calculator. It processes one 8-bit data byte per clock cycle when valid. The polynomial is 0x1021 with an initial value of 0xFFFF. No reflection or final XOR is applied to the output.
This IP provides a compact serial CRC-16-CCITT implementation. It is verified against standard test vectors. It is suitable for integration into communication protocols.
- Choose Open in IDE. RTL Studio loads the packaged workspace for CRC-16-CCITT Serial.
- Read the Verilog module in the editor. The catalog line for this block: CRC-16-CCITT Serial.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
Supports standard CRC-16/CCITT-FALSE algorithm. Accepts 8-bit parallel data input synchronously. Provides a ready flag when the CRC result is computed. Uses a simple shift-and-XOR serial reduction method. Suitable for low-area embedded applications.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input. |
| rst_n | Input | 1 | Active-low asynchronous reset. |
| start | Input | 1 | Start signal for a new CRC calculation sequence. |
| data_in | Input | 8 | Data byte to be processed. |
| data_valid | Input | 1 | Indicates that data_in is valid. |
| crc_ready | Output | 1 | High when the CRC result is available in crc_out. |
| crc_out | Output | 16 | The calculated CRC-16 value. |
Architecture
The module uses a shift register and XOR logic to compute the CRC. It mixes the input data into the CRC state before serial reduction.
Verification
The testbench verifies single-byte and multi-byte sequences. It compares results against known reference values.
| Test Case | Input Data | Expected CRC | Result |
|---|---|---|---|
| Single Byte 0x01 | 0x01 | 0xF1D1 | PASS |
| Single Byte 0x00 | 0x00 | 0xE1F0 | PASS |
| Single Byte 0xFF | 0xFF | 0xFF00 | PASS |
| String "123456789" | 0x31..0x39 | 0x29B1 | PASS |
The simulation log confirms all tests passed. No errors were detected during execution.
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