Code Conversion

4-Bit BCD to Binary Converter — L2 Upgrade

A 4-bit BCD to binary converter with Valid/Ready interface and skid buffer for backpressure handling.

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About this block

Simulate it in the Verilog IDE

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4-Bit BCD to Binary Converter — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4-bit Binary Coded Decimal (BCD) to Binary converter. It uses a Valid/Ready handshaking interface with a skid buffer for backpressure handling. The design is suitable for Level 2 (L2) integration in pipelined systems.

This IP provides a robust BCD to binary conversion with flow control. It is ready for integration into larger digital systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit BCD to Binary Converter — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 4-bit BCD to binary converter with Valid/Ready interface and skid buffer for backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Converts 4-bit BCD input to 8-bit binary output.
Supports Valid/Ready flow control for synchronous data transfer.
Includes a skid buffer to handle backpressure when the downstream is not ready.
Asynchronous reset for initialization.
Verified with Icarus Verilog simulation.

Interface

The module uses a standard Valid/Ready interface.

Signal Name	Direction	Width	Description
clk	input	1	Clock signal
rst_n	input	1	Active-low asynchronous reset
bcd_in	input	[3:0]	4-bit BCD input data
valid_in	input	1	Input valid signal
ready_out	output	1	Output ready signal (high when skid buffer is empty)
bin_out	output	[7:0]	8-bit binary output data
valid_out	output	1	Output valid signal

Architecture

The design consists of a combinatorial conversion logic wrapped in a skid buffer register. The skid buffer holds the input data when the downstream is not ready. When the downstream is ready, the data is pushed to the output. The ready signal is high only when the skid buffer is empty.

Verification

The testbench covers the following scenarios:

Test Case	Description	Expected Result
TC1	Basic Pass-Through	Data passes through immediately when ready is high
TC2	Skid Buffer Hold	Data is held in skid buffer when ready is low
TC3	Invalid BCD Input	Invalid BCD values are passed through as binary
TC4	Reset	All outputs are cleared on reset

All test cases passed successfully in simulation. Use the RtlStudio Waveform tab to inspect signals with sim/dump.vcd.

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