Code Conversion
Binary to Excess-3 4-bit — L1 Upgrade — L2 Upgrade
Glitch-free 4-bit Binary to Excess-3 converter with Valid/Ready skid buffer for backpressure handling.
About this block
Simulate it in the Verilog IDE
Binary to Excess-3 4-bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This Intellectual Property (IP) converts a 4-bit binary input to its 4-bit Excess-3 equivalent. It implements a glitch-free conversion with a Valid/Ready skid buffer for backpressure handling.
The design ensures data integrity during backpressure events by storing incoming data in a skid register, ensuring no data is lost when the downstream consumer is not ready.
This IP provides a robust, glitch-free conversion from 4-bit binary to Excess-3 code. It integrates a registered skid buffer to handle backpressure gracefully, ensuring no data loss when the downstream system is busy. The design is fully verified through simulation, covering basic conversion, backpressure holding, and skid buffer draining scenarios. It is suitable for integration into systems requiring reliable data transfer with flow control.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Binary to Excess-3 4-bit — L1 Upgrade — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: Glitch-free 4-bit Binary to Excess-3 converter with Valid/Ready skid buffer for backpressure handling.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The module consists of two main components:
- Combinational Converter: Adds 3 to the input binary value to produce the Excess-3 code.
- Registered Skid Buffer: Manages flow control when the downstream
readysignal is low. It holds the current output stable while storing the new converted data in an internal register.
Interface
| Signal Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Clock input |
rst_n | Input | 1 | Active-low reset |
data_in | Input | 4 | Binary input data |
valid_in | Input | 1 | Input valid signal |
ready_out | Input | 1 | Ready signal from downstream |
data_out | Output | 4 | Excess-3 output data |
valid_out | Output | 1 | Output valid signal |
Verification
The testbench verifies basic conversion, backpressure handling, and skid buffer draining. All test cases passed successfully in the simulation log.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Basic conversion with valid/ready | PASS |
| TC2 | Backpressure with ready=0 | PASS |
| TC3 | Skid buffer drain | PASS |
| TC4 | Intermittent backpressure | PASS |
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