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8-Bit Priority Decoder (One-Hot to Binary) — L1 Upgrade — L2 Upgrade

An 8-bit priority decoder that converts one-hot input to binary index, featuring registered output, valid/ready interface, and skid buffer for backpressure handling.

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8-Bit Priority Decoder (One-Hot to Binary) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The 8-Bit Priority Decoder is a high-performance digital IP core designed to convert an 8-bit one-hot encoded input vector into a 3-bit binary index. It identifies the most significant bit (MSB) set to logic high in the input, assigning higher priority to higher indices (bit 7 is highest priority).

This design is optimized for pipelined systems, featuring:

  • Registered Output: Meets timing constraints and supports high-frequency operation.
  • Valid/Ready Handshake: Standard flow control protocol for backpressure handling.
  • Skid Buffer: Ensures data integrity by buffering pending results when the output is stalled, preventing data loss.
  • Deterministic Latency: Predictable performance for system timing analysis.

This IP implements an 8-bit priority decoder that converts a one-hot encoded input vector into a 3-bit binary index. It identifies the most significant bit (MSB) set to logic high in the input. The design features a registered output stage with a valid/ready handshake protocol and a skid buffer to handle backpressure, ensuring data integrity in pipelined systems. It provides deterministic latency and robust flow control.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Priority Decoder (One-Hot to Binary) — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: An 8-bit priority decoder that converts one-hot input to binary index, featuring registered output, valid/ready interface, and skid buffer for backpressure handling.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • One-Hot to Binary Conversion: Efficiently maps 8-bit one-hot input to a 3-bit binary index.
  • Priority Logic: Higher indices have higher priority (bit 7 > bit 0).
  • Flow Control: Supports backpressure via valid_in/ready_in handshake.
  • Skid Buffer: Handles output stalls without dropping input data.
  • Asynchronous Reset: Active-low reset (rst_n) for synchronous initialization.
  • Verified: Comprehensive testbench coverage with Icarus Verilog simulation.

Interface

Signal NameDirectionWidthDescription
clkInput1Clock signal
rst_nInput1Asynchronous active-low reset
data_inInput8One-hot encoded input vector
valid_inInput1Input valid signal (asserted when data_in is valid)
ready_inInput1Output ready signal (driven by downstream consumer)
valid_outOutput1Output valid signal (asserted when result is valid)
resultOutput3Binary index of the highest priority bit

Architecture

The design consists of two main parts:

  1. Combinational Priority Encoder: Finds the MSB of data_in.
  2. Registered Stage with Skid Buffer: Handles valid/ready handshaking and stores pending data in a skid buffer when ready_in is low.

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