Code Conversion

N-bit Priority Encoder — L1 Upgrade — L2 Upgrade

N-bit priority encoder with registered output and valid/ready skid buffer for flow control.

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About this block

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N-bit Priority Encoder — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust priority encoder with flow control.

It is suitable for systems requiring deterministic latency and back-pressure handling.

The skid buffer ensures data integrity during stalls, making it ideal for high-throughput data paths where consumer readiness may vary.

Choose Open in IDE. RTL Studio loads the packaged workspace for N-bit Priority Encoder — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: N-bit priority encoder with registered output and valid/ready skid buffer for flow control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Priority Encoding: Encodes the index of the highest set bit in an 8-bit vector.
MSB-First Priority: Bit 7 has the highest priority, down to Bit 0.
Registered Output: Improves timing closure by registering the output index and valid signal.
Flow Control: Implements a valid/ready handshake with a skid buffer to handle back-pressure.
Synchronous Reset: All internal registers are reset synchronously using an active-low reset signal.

Interface

The module uses a standard valid/ready handshake protocol. The module acts as a Producer (Master) driving valid_out and index_out. The ready_in signal is an Input from the downstream consumer, indicating it is ready to accept data.

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low synchronous reset
`data_in`	Input	8	Input data vector to be encoded
`valid_in`	Input	1	Input valid signal (asserted when `data_in` is valid)
`ready_in`	Input	1	Ready signal from downstream consumer (asserted when consumer can accept data)
`valid_out`	Output	1	Output valid signal (asserted when `index_out` is valid)
`index_out`	Output	3	Encoded index of the highest priority set bit

Architecture

The design consists of a combinational priority encoder and a registered output stage. A skid buffer holds data when the ready_in signal is deasserted, preventing data loss.

Verification

The provided testbench covers basic encoding, skid buffer behavior, and back-to-back transactions.

Test Case	Description	Expected Result
TC1a	Single bit 0 set	`index_out` = 0, `valid_out` = 1
TC1b	Single bit 7 set	`index_out` = 7, `valid_out` = 1
TC1c	Bits 0 and 7 set	`index_out` = 7, `valid_out` = 1
TC1d	No bits set	`valid_out` = 0
TC2a	Stall with valid data	`valid_out` = 0 (initially)
TC2b	Release stall	`index_out` = 0, `valid_out` = 1
TC2c	Stall with new data	Skid buffer updates
TC2d	Release stall with new data	`index_out` = 2, `valid_out` = 1
TC3a	Back-to-back bit 0	`index_out` = 0, `valid_out` = 1
TC3b	Back-to-back bit 1	`index_out` = 1, `valid_out` = 1

All test cases passed successfully in simulation.

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