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Code Conversion

Binary→Thermometer Compare-Gen (8→9)

Generate-for compare converter from 8-bit binary to a 9-bit thermometer code slice.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Binary→Thermometer Compare-Gen (8→9) is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core converts an 8-bit binary input into a 9-bit thermometer code output. It is designed for simple digital logic applications requiring unary representation, such as DAC control or simple priority encoders.

This module provides a reliable, synthesizable conversion from 8-bit binary to 9-bit thermometer code. It is suitable for low-complexity digital systems and has been fully verified using Icarus Verilog.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Binary→Thermometer Compare-Gen (8→9).
  2. Read the Verilog module in the editor. The catalog line for this block: Generate-for compare converter from 8-bit binary to a 9-bit thermometer code slice.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Full Range Support: Accepts 8-bit input (0-255).
  • Thermometer Output: Produces a 9-bit output where the number of set bits equals the input value.
  • Efficient Implementation: Uses a generate loop for clean, synthesizable logic.
  • Verified: Fully tested with Icarus Verilog simulation covering edge cases and intermediate values.

Ports

Port NameDirectionWidthDescription
bin_inInput[7:0]8-bit binary input value
thermo_outOutput[8:0]9-bit thermometer code output

Verification

The testbench covers ten distinct test cases including edge values:

  • Input 0 results in all zeros in the output.
  • Input 1 sets only the least significant bit.
  • Input 255 sets all output bits to one.
  • Intermediate values like 3, 4, 7, 8, 127, and 128 are also verified.

All tests passed successfully in the simulation log.

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