Code Conversion

4-Bit Binary to BCD Converter (Shift-and-Add-3)

A synchronous 4-bit binary to BCD converter using the shift-and-add-3 algorithm with FSM control.

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About this block

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4-Bit Binary to BCD Converter (Shift-and-Add-3) is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a synchronous Finite State Machine (FSM) that converts a 4-bit binary input (0-15) into a 2-digit BCD output (00-15) using the Shift-and-Add-3 algorithm. It is designed for low resource utilization and educational purposes, featuring a simple handshake protocol (start/done) and asynchronous reset. The design is fully verified for all 16 input combinations.

This document provides a complete overview of the 4-Bit Binary to BCD Converter IP core. It details the architectural FSM, port definitions, integration steps, and verification results. The core is designed for simplicity and educational value, implementing the Shift-and-Add-3 algorithm with a synchronous handshake interface. Users should refer to the Appendix for code structure and implementation specifics.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Binary to BCD Converter (Shift-and-Add-3).
Read the Verilog module in the editor. The catalog line for this block: A synchronous 4-bit binary to BCD converter using the shift-and-add-3 algorithm with FSM control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Algorithm: Shift-and-Add-3 (standard BCD conversion method).
Input: 4-bit binary value (bin_in).
Output: 8-bit BCD value (bcd_out), where upper nibble is tens and lower nibble is units.
Interface: Synchronous clock (clk), asynchronous active-low reset (rst_n), start pulse (start), and completion flag (done).
Latency: 4 conversion cycles + 1 load cycle (6 cycles total from start to done).
Verification: Fully tested with Icarus Verilog simulation covering all input cases.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	System clock signal
`rst_n`	Input	1	Asynchronous active-low reset
`bin_in`	Input	4	4-bit binary input value (0-15)
`start`	Input	1	Start conversion pulse (high for 1 cycle)
`bcd_out`	Output	8	8-bit BCD output (Tens[3:0], Units[3:0])
`done`	Output	1	High when conversion is complete

Architecture

The converter operates using a 4-state FSM: IDLE, SHIFT, ADD, and LOAD.

### Operation Sequence

IDLE: Waits for the start signal. Upon detection, initializes the BCD register to 0 and resets the bit counter.
SHIFT: Shifts the BCD register left by 1 bit and loads the next bit from bin_in into the LSB.
ADD: Checks both nibbles of the BCD register. If a nibble is >= 5, adds 3 to correct the BCD value. Increments the bit counter.
LOAD: If all 4 bits have been processed, assigns the final BCD value to bcd_out and asserts done. Returns to IDLE.

Integration

### Instantiation

To use this IP in your design, instantiate the module binary_to_bcd_4bit_shift_add3:

### Usage Protocol

Assert start for one clock cycle when done is low.
Wait until done goes high.
Read bcd_out. The value is valid only when done is high.
Deassert start before the next conversion.

Verification

The included testbench (tb_binary_to_bcd_4bit_shift_add3.v) iterates through all 16 possible input values (0 to 15). It asserts start, waits for the done signal, and compares bcd_out against expected values.

### Running Simulation

Ensure Icarus Verilog is installed.
Run the simulation script:
Check the output log for INFO: PASS. All 16 test cases must pass.

### Test Results

Test Case	Input (bin)	Expected BCD	Result
0	0000	0000_0000	PASS
1	0001	0000_0001	PASS
5	0101	0000_0101	PASS
9	1001	0000_1001	PASS
10	1010	0001_0000	PASS
15	1111	0001_0101	PASS

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