Code Conversion

Gray-Code Incrementer 8-Bit

Registered 8-bit Gray code incrementer with Gray-to-binary and binary-to-Gray conversion logic.

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About this block

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Mediumverilogsimsyn

Gray-Code Incrementer 8-Bit is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a registered 8-bit Gray code incrementer. It ensures single-bit transitions between consecutive values, making it ideal for asynchronous FIFO pointers and rotary encoder interfaces.

The design features single-cycle latency and supports active-low reset. It converts the input Gray code to binary, increments the value, and converts it back to Gray code.

The module implements a sequential Gray code counter with a single-cycle latency. It accepts an 8-bit Gray code input and produces the next Gray code value in the sequence.

Gray-to-binary conversion: Transforms the input Gray code into a binary representation.
Binary incrementation: Increments the binary value by one.
Binary-to-Gray conversion: Transforms the incremented binary value back into Gray code.

Choose Open in IDE. RTL Studio loads the packaged workspace for Gray-Code Incrementer 8-Bit.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-bit Gray code incrementer with Gray-to-binary and binary-to-Gray conversion logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of three main combinational stages followed by a registered output stage.

### 1. Gray-to-Binary Conversion The input Gray code is converted to a binary representation.

The most significant bit (MSB) remains unchanged.
Each lower binary bit is the XOR of the corresponding Gray bit and the next higher binary bit.

### 2. Binary Increment The binary value is incremented by one using standard addition.

### 3. Binary-to-Gray Conversion The incremented binary value is converted back to Gray code.

The MSB remains unchanged.
Each lower Gray bit is the XOR of the corresponding binary bit and the next higher binary bit.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`gray_in`	Input	8	Input Gray code
`gray_out`	Output	8	Output Gray code

Verification

The testbench verifies the following scenarios:

TC1: Basic Increment from 0.
TC2: Increment from Binary 5.
TC3: Wrap around from Max Value.
TC4: Full Cycle Walk.

All test cases passed successfully.

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