RTL Studio Open IDE

Code Conversion

N-Bit Gray to Binary Decoder

Converts N-bit Gray code input to corresponding Binary output using a combinational XOR reduction chain.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

N-Bit Gray to Binary Decoder is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This module provides a parameterizable, purely combinational solution for converting N-bit Gray code inputs to their corresponding Binary outputs. It utilizes an XOR reduction chain to ensure minimal logic depth and area overhead. The core logic is purely combinational.

The core functionality converts a Gray code vector gray_in to a Binary vector bin_out. The conversion algorithm relies on the property that the Most Significant Bit (MSB) of the binary output is identical to the MSB of the Gray input. Each subsequent binary bit is calculated as the XOR of the next higher binary bit and the current Gray bit.

Algorithm:

  • bin[MSB] = gray[MSB]
  • bin[i] = bin[i+1] ^ gray[i] for i < MSB
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for N-Bit Gray to Binary Decoder.
  2. Read the Verilog module in the editor. The catalog line for this block: Converts N-bit Gray code input to corresponding Binary output using a combinational XOR reduction chain.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design is implemented using a generate loop to support parameterizable widths. The logic propagates the XOR operation from the MSB to the LSB, ensuring that each bit depends only on the bits above it in the binary representation.

  • Combinational Logic: The data path is purely combinational.
  • Parameterizable: The width of the input/output vectors is controlled by the WIDTH parameter.
  • Interface Compatibility: Clock and reset ports are included to maintain consistency with synchronous design templates, though they do not affect the combinational behavior.

Interface

Port NameDirectionWidthDescription
gray_inInputWIDTHN-bit Gray code input vector.
bin_outOutputWIDTHN-bit Binary code output vector.

Parameters

ParameterDefaultDescription
WIDTH8The bit-width of the Gray and Binary vectors.

Verification

The provided testbench (tb_gray_decoder) performs self-checking verification to ensure correctness.

  • Coverage: Tests all 16 combinations for a 4-bit width.
  • Edge Cases: Validates all-zeros and all-ones patterns for the default 8-bit width.
  • Validation: Compares the output against known Gray-to-Binary conversion tables.

To run the simulation, execute the provided script or command in your EDA tool. The log should indicate PASS for all test cases.

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