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16-Bit Priority Encoder — L1 Upgrade — L2 Upgrade

16-bit priority encoder with registered outputs and Valid/Ready skid buffer for backpressure handling.

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About this block

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16-Bit Priority Encoder — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 16-bit priority encoder that identifies the index of the highest-priority set bit in a 16-bit input vector.

It features registered outputs and a Valid/Ready handshake interface with a skid buffer to handle backpressure without data loss.

The design ensures minimal latency for the combinational logic while maintaining data integrity under flow control constraints.

valid_in: Asserted by the producer when data is valid.
ready_out: Asserted by the consumer when it can accept data.
valid_out: Asserted when the encoder has a valid result to send.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Priority Encoder — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 16-bit priority encoder with registered outputs and Valid/Ready skid buffer for backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Input Processing: Encodes the highest set bit index.
Registered Outputs: index_out and valid_out are registered to improve timing.
Valid/Ready Handshake: Supports backpressure via a skid buffer.
Low Latency: Combinational priority logic for immediate encoding.
Synchronous Reset: Active-low synchronous reset for all internal registers.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`data_in`	Input	[15:0]	Input data vector
`valid_in`	Input	1	Input valid signal (producer ready)
`ready_out`	Input	1	Output ready signal (consumer ready)
`index_out`	Output	[3:0]	Encoded index of highest set bit
`valid_out`	Output	1	Output valid signal

Architecture

The design consists of two main stages:

Combinational Priority Encoder: Determines the highest set bit index and validity.
Registered Output with Skid Buffer: Manages the Valid/Ready handshake, holding data if the output is not ready.

The encoder determines the highest set bit index. It outputs a 4-bit index and a valid flag. The skid buffer manages the Valid/Ready handshake. It holds new data if the output is not ready. It releases held data when the output becomes ready.

Verification

The testbench validates reset behavior and encoding accuracy. It checks basic priority encoding for bits 0 and 15. It verifies skid buffer hold and release operations. It confirms output deassertion when input is invalid.

Test Case	Description
TC1	Reset check
TC2	Basic priority encoding bit 15
TC3	Basic priority encoding bit 0
TC4	Skid hold output check
TC5	Skid release check
TC6	Skid hold output check 2
TC7	Skid release check 2
TC8	No valid input check

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