Code Conversion

One-Hot→Binary MSB-Priority OR Tree (8→3) — L1 Upgrade

Registered 8-to-3 one-hot to binary encoder with MSB priority and validity check.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

One-Hot→Binary MSB-Priority OR Tree (8→3) — L1 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core converts an 8-bit one-hot input vector into a 3-bit binary output.

It implements an MSB-priority encoding scheme, where the highest-indexed active bit determines the output value.

The design is fully registered and pipelined to ensure timing closure in high-frequency applications.

Choose Open in IDE. RTL Studio loads the packaged workspace for One-Hot→Binary MSB-Priority OR Tree (8→3) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-to-3 one-hot to binary encoder with MSB priority and validity check.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Conversion: 8-bit one-hot to 3-bit binary.
Priority: MSB priority (Bit 7 is highest, Bit 0 is lowest).
Pipelining: Registered outputs with synchronous reset for improved timing.
Validation: Parity-based check to ensure exactly one input bit is set.
Logic: Combinational OR-tree for encoding.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`one_hot_in`	Input	[7:0]	8-bit one-hot input vector
`binary_out`	Output	[2:0]	3-bit binary encoded output
`valid_out`	Output	1	High if exactly one bit in `one_hot_in` is set

Verification

The included testbench (tb_one_hot_to_binary_8to3_msb_priority_registered_pipelined.v) verifies:

All 8 valid one-hot inputs (bits 0-7).
Two invalid cases: all zeros and multiple bits set.

### Test Case Table

Test Case	Input	Expected Binary	Expected Valid	Result
TC1	8'b10000000	3'b111	1'b1	PASS
TC2	8'b00000001	3'b000	1'b1	PASS
TC3	8'b00010000	3'b100	1'b1	PASS
TC4	8'b00001000	3'b011	1'b1	PASS
TC5	8'b01000000	3'b110	1'b1	PASS
TC6	8'b00100000	3'b101	1'b1	PASS
TC7	8'b00000100	3'b010	1'b1	PASS
TC8	8'b00000010	3'b001	1'b1	PASS
TC9	8'b11000000	X	1'b0	PASS
TC10	8'b00000000	X	1'b0	PASS

### Expected Simulation Results

Run the simulation to see the following log output:

More in Code Conversion

All Code Conversion blocks