Code Conversion

8-Bit to 16-Bit Sign Extender

Combinational logic module that sign-extends an 8-bit input to a 16-bit output by replicating the MSB.

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About this block

Simulate it in the Verilog IDE

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8-Bit to 16-Bit Sign Extender is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

An open-source, purely combinational Verilog IP core that performs sign extension from 8 bits to 16 bits. It replicates the most significant bit (MSB) of the input into the upper 8 bits of the output, ensuring correct two's complement representation for both positive and negative numbers.

This IP provides a simple, efficient, and verified mechanism for 8-bit to 16-bit sign extension. It is suitable for arithmetic operations requiring width conversion in digital signal processing or general-purpose ALU designs. The design is purely combinational with no internal state, ensuring zero latency overhead beyond gate delay. All boundary conditions of 8-bit two's complement numbers (from -128 to +127) have been verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit to 16-Bit Sign Extender.
Read the Verilog module in the editor. The catalog line for this block: Combinational logic module that sign-extends an 8-bit input to a 16-bit output by replicating the MSB.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module consists of a single Device Under Test (DUT) with direct signal mapping. It uses concatenation to replicate the sign bit.

Interface

The following table defines the port interface.

Port Name	Direction	Width	Description
`in_data`	Input	8	8-bit input data
`out_data`	Output	16	16-bit sign-extended output

Verification

The testbench covers standard sign extension cases, including boundary conditions. All 6 test cases passed successfully.

Test Case	Input	Expected Output	Result
TC1	0x05	0x0005	PASS
TC2	0xF5	0xFFF5	PASS
TC3	0x00	0x0000	PASS
TC4	0xFF	0xFFFF	PASS
TC5	0x80	0xFF80	PASS
TC6	0x7F	0x007F	PASS

Expected Log Output:

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