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Binary→Thermometer LUT (4→15, Case) — L1 Upgrade — L2 Upgrade

A registered 4-bit to 15-bit thermometer code converter with valid/ready interface and skid buffer for backpressure handling.

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About this block

Simulate it in the Verilog IDE

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Binary→Thermometer LUT (4→15, Case) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core converts a 4-bit binary input into a 15-bit thermometer-encoded output. It features a registered output path for improved timing closure and a Valid/Ready interface with a skid buffer to handle backpressure gracefully.

This IP provides a robust binary-to-thermometer conversion with flow control.

The registered output and skid buffer ensure reliable operation in pipelined designs.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Binary→Thermometer LUT (4→15, Case) — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: A registered 4-bit to 15-bit thermometer code converter with valid/ready interface and skid buffer for backpressure handling.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Input: 4-bit binary vector (data_in[3:0]).
  • Output: 15-bit thermometer vector (data_out[14:0]).
  • Interface: AXI-like Valid/Ready handshaking.
  • Skid Buffer: Prevents data loss when the consumer is not ready (ready_in is low).
  • Registered Output: Improves timing closure by registering the final output.
  • Reset: Active-low synchronous reset (rst_n).

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low reset
valid_inInput1Input valid signal
data_inInput[3:0]4-bit binary input
ready_inInput1Output ready signal
valid_outOutput1Output valid signal
data_outOutput[14:0]15-bit thermometer output

Architecture

The module consists of three main stages:

  1. Combinational LUT: Maps the 4-bit input to a 15-bit thermometer pattern using a case statement.
  2. Skid Buffer: Stores the input data (data_in) and a valid flag when ready_in is deasserted. This ensures no data is lost during backpressure.
  3. Registered Output: Registers the LUT result or the skid buffer data to produce valid_out and data_out.

### Data Flow

  • If valid_in is high and ready_in is high, the data passes through the LUT and is registered.
  • If valid_in is high and ready_in is low, the data is stored in the skid buffer. valid_out remains low.
  • When ready_in becomes high, the skid buffer drains its stored data to the output.

Verification

The testbench verifies:

  • TC1: Basic pass-through for all 16 input values (0-15).
  • TC2: Backpressure hold and drain logic.

All tests are designed to pass successfully under normal operating conditions.

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