Code Conversion

One-Hot→Binary Case Decode (4→2) — L1 Upgrade — L2 Upgrade

A registered one-hot to binary decoder with valid/ready handshaking and skid buffer for backpressure handling.

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About this block

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One-Hot→Binary Case Decode (4→2) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) core converts a 4-bit one-hot encoded input signal into a 2-bit binary output. It is designed for high-performance applications such as L1/L2 cache tag decoding or priority arbitration.

### Key Features

One-Hot to Binary Conversion: Maps 4 one-hot bits to 2-bit binary codes.
Valid/Ready Handshaking: Implements AXI-like flow control for seamless integration into pipelined systems.
Skid Buffer: Handles backpressure gracefully when the downstream ready signal is deasserted, ensuring no data loss.
Registered Output: Provides clean timing margins for downstream logic.
Robust Error Handling: Defaults to zero output for invalid or all-zero one-hot inputs.

This IP provides a robust, flow-controlled one-hot to binary conversion.

Choose Open in IDE. RTL Studio loads the packaged workspace for One-Hot→Binary Case Decode (4→2) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A registered one-hot to binary decoder with valid/ready handshaking and skid buffer for backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of two main stages:

Combinational Decoder: Instantly maps the one_hot_in to a binary value.
Registered Pipeline Stage with Skid Buffer: Latches the decoded value and valid status only when valid_in and ready_in are both asserted. If ready_in is low, the skid buffer holds the previous valid data.

### Block Diagram

Interface

Signal	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low reset
`one_hot_in`	Input	4	One-hot encoded input (e.g., 4'b0001)
`valid_in`	Input	1	Input data is valid
`ready_in`	Input	1	Downstream is ready to accept data
`binary_out`	Output	2	Decoded binary output
`valid_out`	Output	1	Output data is valid

Verification

The testbench (tb/tb_one_hot_to_binary_4to2_case_registered_pipelined_valid_ready_skid.v) covers:

Reset Behavior: Ensures registers clear to zero.
Basic Decoding: Verifies all 4 one-hot cases.
Backpressure: Tests skid buffer holding data when ready_in is low.
Invalid Inputs: Handles all-zero one-hot inputs correctly.

### Running Simulation

Expected output:

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