RTL Studio Open IDE

Code Conversion

8-to-16 Zero Extension — L1 Upgrade

Registered 8-to-16 bit zero extension with enable control and valid handshake.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-to-16 Zero Extension — L1 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) implements a registered 8-to-16 bit zero extension module with enable control and a valid handshake signal. It is designed for low-latency data width expansion in synchronous systems, specifically targeting Level 1 (L1) cache or buffer upgrades where data integrity and synchronization are critical.

### Key Features

  • Registered Output: Data is latched on the positive clock edge, ensuring synchronous system integration.
  • Zero Extension: Automatically pads the upper 8 bits of the 16-bit output with zeros.
  • Enable Control: Gates data propagation; output holds its state when en is low.
  • Valid Handshake: A valid signal indicates when the output data is stable and ready for consumption.
  • Asynchronous Reset: Active-low reset clears both data and valid signals immediately.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-to-16 Zero Extension — L1 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Registered 8-to-16 bit zero extension with enable control and valid handshake.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

PortDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
enInput1Enable signal (high to propagate data)
dinInput[7:0]8-bit data input
validOutput1High when output data is valid
doutOutput[15:0]16-bit zero-extended data output

Integration

### Instantiation Example

### Timing Behavior

  • Reset: When rst_n is low, valid and dout are forced to 0.
  • Enable High: On the next positive clock edge, valid goes high, and dout becomes {8'b0, din}.
  • Enable Low: valid goes low, and dout is cleared to 0 (as per RTL implementation).

Verification

The provided testbench (tb/tb_zero_extend_enable_registered_8to16.v) covers the following scenarios:

  1. TC1: Reset State: Verifies that valid and dout are zero after reset deassertion.
  2. TC2: Enable Data (0xAB): Checks propagation of 0xAB with zero extension.
  3. TC3: Enable Data (0xFF): Checks propagation of 0xFF with zero extension.
  4. TC4: Disable State: Verifies behavior when enable is toggled off.
  5. TC5: Zero Extension: Confirms upper 8 bits of dout are always zero.

### Running Simulation

  1. Compile: Compile the RTL and Testbench using your preferred simulator (e.g., iverilog, vcs, or modelsim).
  2. Run: Execute the simulation.
  3. Check Results: Look for the following output in the console:

More in Code Conversion

All Code Conversion blocks