RTL Studio Open IDE

Code Conversion

4-Bit Thermometer to Binary Encoder

Converts a 4-bit thermometer code to a 2-bit binary value with clamping for overflow.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

4-Bit Thermometer to Binary Encoder is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a combinational logic block that converts a 4-bit thermometer code into a 2-bit binary value. It is designed for low-complexity digital systems requiring efficient code conversion. The module includes saturation clamping to handle invalid inputs (values > 3) by outputting the maximum representable 2-bit value (3), preventing overflow in downstream logic. The design is fully synthesizable, verified with Icarus Verilog, and ready for integration into larger SoC or FPGA projects.

The encoder accepts a 4-bit input (thermometer_in) where the number of high bits indicates the magnitude. It produces a 2-bit binary output (binary_out).

  • Input Range: 0 to 15 (4-bit)
  • Output Range: 0 to 3 (2-bit)
  • Clamping Behavior: If the input represents a value greater than 3 (i.e., 4 or more bits are set), the output is clamped to 2'b11 (3).

This behavior ensures that downstream 2-bit logic does not encounter undefined or overflow states.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Thermometer to Binary Encoder.
  2. Read the Verilog module in the editor. The catalog line for this block: Converts a 4-bit thermometer code to a 2-bit binary value with clamping for overflow.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
thermometer_inInput[3:0]4-bit thermometer encoded input
binary_outOutput[1:0]2-bit binary encoded output

Integration

### Instantiation Example (Verilog)

### Simulation

The design includes a self-checking testbench (tb/tb_thermometer_to_binary_4b.v).

To run the simulation:

  1. Ensure Icarus Verilog (iverilog) is installed.
  2. Run the following commands in the project root:
  3. Check the console output for INFO: PASS messages.
  4. A VCD file (sim/dump.vcd) is generated for waveform analysis.

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