Code Conversion

Pipelined Gray↔Binary Register 8-bit

Synchronous 8-bit register performing bidirectional Gray code and Binary code conversion with enable and reset controls.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Pipelined Gray↔Binary Register 8-bit is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A synchronous 8-bit register IP core that performs bidirectional conversion between Gray code and Binary code. Designed for low-latency applications requiring error-resistant data transmission or position sensing.

This IP provides a verified, pipelined method for converting between 8-bit Gray and Binary codes.

It supports configurable direction via a mode control signal, synchronous enable, and active-low reset.

Choose Open in IDE. RTL Studio loads the packaged workspace for Pipelined Gray↔Binary Register 8-bit.
Read the Verilog module in the editor. The catalog line for this block: Synchronous 8-bit register performing bidirectional Gray code and Binary code conversion with enable and reset controls.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Bidirectional Conversion: Converts Gray-to-Binary and Binary-to-Gray.
Pipelined Architecture: Combinatorial logic followed by registered outputs for improved timing.
Control Signals: Synchronous enable (en) and active-low synchronous reset (rst_n).
Configurable Mode: Single bit (mode) selects input/output direction.
Verified: Fully simulated with Icarus Verilog.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset input
`en`	Input	1	Synchronous enable input
`gray_in`	Input	[7:0]	Gray code input data
`bin_in`	Input	[7:0]	Binary code input data
`mode`	Input	1	Conversion mode select (0: Gray->Bin, 1: Bin->Gray)
`bin_out`	Output	[7:0]	Binary code output data
`gray_out`	Output	[7:0]	Gray code output data

Architecture

The module consists of two parallel combinatorial conversion blocks and a registered output stage. The mode signal selects which input path is active and which output is driven.

Integration

### Instantiation

### Simulation

To run the simulation, ensure Icarus Verilog is installed.

Verification

The testbench covers reset behavior, enable bubbles, and multiple conversion cases for both modes. All test cases passed successfully in the simulation run.

Test Case	Description	Result
TC1a-e	Gray to Binary conversions	PASS
TC2a-e	Binary to Gray conversions	PASS
TC3a-c	Enable hold and re-enable checks	PASS
TC4a	Reset behavior check	PASS

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