Code Conversion

Thermometer-to-Binary Encoder — L1 Upgrade

A pipelined module that converts a 16-bit thermometer code into a 4-bit binary index.

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About this block

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Mediumverilogsimsyn

Thermometer-to-Binary Encoder — L1 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core converts a 16-bit thermometer code into a 4-bit binary value. It utilizes a one-stage pipelined architecture to register inputs and outputs, ensuring low latency and predictable timing suitable for Level 1 (L1) upgrade scenarios.

The design identifies the most significant bit (MSB) set in the input vector and outputs its index as a 4-bit binary number. This approach minimizes critical path delay by separating the sampling logic from the combinational decoding logic.

Choose Open in IDE. RTL Studio loads the packaged workspace for Thermometer-to-Binary Encoder — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A pipelined module that converts a 16-bit thermometer code into a 4-bit binary index.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Input: 16-bit thermometer code (data_in[15:0]).
Output: 4-bit binary index (data_out[3:0]).
Pipelining: One-stage pipeline with input and output registers.
Control: Asynchronous active-low reset (rst_n) and valid flag (valid_in/valid_out).
Logic: Combinational MSB detection logic between pipeline stages.
Latency: 1 clock cycle (combinational logic is registered).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`valid_in`	Input	1	Input valid signal
`data_in`	Input	[15:0]	Thermometer code input
`valid_out`	Output	1	Output valid signal
`data_out`	Output	[3:0]	Binary encoded output

Architecture

The design follows a classic two-stage pipeline:

Input Register Stage: Captures data_in and valid_in on the rising edge of clk. This isolates the external interface from the combinational logic, improving timing closure.
Combinational Logic: Performs a priority-encoded search for the Most Significant Bit (MSB) set in the registered input. The logic uses a cascaded ternary operator structure to determine the binary index.
Output Register Stage: Registers the computed binary result and the valid flag, providing a stable output for downstream logic.

Verification

The verification environment includes a testbench (tb_thermometer_bin_pipeline.v) that covers seven specific test cases to ensure functional correctness.

### Test Cases

Test Case	Input Condition	Expected Output	Result
TC1	All zeros	`data=0`, `valid=1`	PASS
TC2	Bit 0 set	`data=0`, `valid=1`	PASS
TC3	Bit 15 set	`data=15`, `valid=1`	PASS
TC4	Bit 7 set	`data=7`, `valid=1`	PASS
TC5	All bits set	`data=15`, `valid=1`	PASS
TC6	Valid low	`valid=0`	PASS
TC7	Reset asserted	`data=0`, `valid=0`	PASS

### Simulation Results

Upon running the simulation, the log panel should display:

TC1 PASS valid_out=1, data_out=0
TC2 PASS valid_out=1, data_out=0
TC3 PASS valid_out=1, data_out=15
TC4 PASS valid_out=1, data_out=7
TC5 PASS valid_out=1, data_out=15
TC6 PASS valid_out=0
TC7 PASS valid_out=0, data_out=0 during reset
Simulation ends with INFO: PASS.

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