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Thermometer Select 8-Bit — L1 Upgrade

Registered pipelined thermometer-to-binary encoder for 8-bit inputs with valid flag synchronization.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Thermometer Select 8-Bit — L1 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a registered, pipelined priority encoder that converts an 8-bit thermometer code into a 3-bit binary index.

Designed for low-latency applications, it provides a single-cycle latency with registered outputs to ensure timing closure in synchronous designs.

The core includes a valid flag to synchronize data availability and handles invalid thermometer codes by defaulting to index 0.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Thermometer Select 8-Bit — L1 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Registered pipelined thermometer-to-binary encoder for 8-bit inputs with valid flag synchronization.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Conversion: 8-bit thermometer input to 3-bit binary index.
  • Latency: 1 clock cycle (registered output).
  • Synchronization: valid_in/valid_out handshake for data synchronization.
  • Error Handling: Invalid non-single-bit codes default to index 0.
  • Reset: Active-low asynchronous reset.
  • Verification: Fully verified with 6 test cases covering reset, valid codes, invalid codes, and valid flag transitions.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low reset
thermometer_inInput8Thermometer code input
valid_inInput1Valid input flag
index_outOutput3Binary index output
valid_outOutput1Valid output flag

Integration

### Files

  • rtl/thermometer_select_registered_pipelined_8bit.v: Main RTL source.
  • tb/tb_thermometer_select_registered_pipelined_8bit.v: Testbench for verification.

### Usage

  1. Include rtl/thermometer_select_registered_pipelined_8bit.v in your project.
  2. Instantiate the module with your clock and reset signals.
  3. Drive thermometer_in with a valid thermometer code (single bit set) or handle invalid codes as per the spec.
  4. Assert valid_in to enable data processing.

### Example Instantiation

Limitations

  • Input Format: Assumes thermometer coding (single bit set). Non-thermometer inputs are not guaranteed to produce correct binary indices (defaults to 0).
  • Latency: Fixed at 1 cycle. Not suitable for ultra-low latency requirements where combinational logic is preferred.

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