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Trailing-One Encoder 8-bit — L1 Upgrade

Registered pipeline for encoding the index of the first trailing one in an 8-bit input vector.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Trailing-One Encoder 8-bit — L1 Upgrade is a Verilog reference block in the Code Conversion catalog. Encoders, decoders, priority encoders, and binary/gray converters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered, low-latency trailing-one encoder for 8-bit vectors.

It identifies the index of the least significant bit (LSB) set to '1' and outputs the result on the next clock cycle.

This module is ideal for applications requiring fast priority encoding with synchronous output, such as interrupt controllers or memory management units.

  • Input Width: 8 bits.
  • Output Width: 3 bits (indices 0-7).
  • Latency: 1 cycle (registered output).
  • Priority: LSB (bit 0) has highest priority.
  • Reset: Synchronous active-low reset.
  • Valid Logic: valid_out is asserted when valid_in is asserted.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Trailing-One Encoder 8-bit — L1 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Registered pipeline for encoding the index of the first trailing one in an 8-bit input vector.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of two main stages:

  1. Combinational Priority Encoder: Determines the index of the first set bit in data_in.
  2. Registered Output Stage: Captures the combinational result and valid status on the positive clock edge, synchronized with rst_n.

Verification

The provided testbench (tb_trailing_one_encoder_8bit.v) verifies the encoder against standard test cases.

### Test Cases

Test CaseInput DataExpected IndexDescription
TC10x010LSB set
TC20x807MSB set
TC30x00N/ANo bits set (valid=0)
TC40x021Bit 1 set
TC50x042Bit 2 set
TC6Reset0Reset condition
TC70xFF0All bits set (LSB priority)

### Running Simulation

  1. Ensure ModelSim/Vivado/Verilator is installed.
  2. Run the simulation script provided in the sim/ directory.
  3. Check the log output for "PASS" messages for each test case.

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