Coding & Line Codes

Additive Scrambler 8-bit — L2 Upgrade

8-bit additive scrambler with sync lock detection using standard LFSR polynomial.

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About this block

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Additive Scrambler 8-bit — L2 Upgrade is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit additive scrambler with synchronization lock detection.

It utilizes a standard 8-bit Linear Feedback Shift Register (LFSR) for data whitening and includes logic to detect when the LFSR state matches a specific sync pattern (0x55).

This IP is suitable for basic data whitening applications in serial communication links where synchronization recovery is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for Additive Scrambler 8-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit additive scrambler with sync lock detection using standard LFSR polynomial.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Parallel Key Load: Allows dynamic initialization of the LFSR seed via key_in and load_key.
Serial Data Processing: Processes serial data input (data_in) and outputs scrambled data (data_out).
Sync Lock Detection: Asserts lock signal when the LFSR state equals 0x55.
Asynchronous Reset: Active-low reset (rst_n) initializes the LFSR to zero.
Verilog-2001 Compatible: Uses standard syntax compatible with most modern synthesis tools.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`load_key`	Input	1	Assert to load `key_in` into LFSR
`key_in`	Input	8	Seed data for LFSR initialization
`data_in`	Input	1	Serial data to be scrambled
`data_out`	Output	1	Scrambled serial data
`lock`	Output	1	Sync lock indicator (1 if LFSR == 0x55)

Architecture

The scrambler is built around an 8-bit Linear Feedback Shift Register (LFSR). The feedback polynomial is $x^8 + x^6 + x^5 + x^4 + 1$. Feedback is calculated by XORing taps at bits 7, 5, 4, and 3.

State Update: The LFSR state shifts right on every rising clock edge. The calculated feedback bit is inserted into the LSB.
Scrambling: The output data_out is generated by XORing data_in with the MSB of the LFSR (lfsr[7]).
Lock Detection: The lock signal is asserted if the current LFSR state equals 0x55 (binary 01010101).

Verification

The included testbench (tb_additive_scrambler_lock_8.v) verifies the following behaviors using Icarus Verilog:

TC1: Reset behavior (LFSR clears, lock deasserts).
TC2: Scrambling logic correctness.
TC3: Lock detection when LFSR state matches 0x55.
TC4: Lock loss when LFSR state diverges from 0x55.
TC5: Re-lock acquisition after reloading the key.

### Running Simulation

To verify the IP, run the testbench:

Expected output indicates all test cases passed:

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