Coding & Line Codes

8-Bit Run-Length Decoder (RLE)

An 8-bit Run-Length Decoder that repeats an input value for a specified count.

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About this block

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8-Bit Run-Length Decoder (RLE) is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit Run-Length Decoder (RLE). It accepts a count and a value on input. It outputs the value repeatedly for the specified count cycles. The decoder supports asynchronous reset and synchronous control.

This IP provides a simple and efficient 8-bit Run-Length Decoder. It is suitable for basic data compression or decompression tasks. The design is fully verified with a comprehensive testbench.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Run-Length Decoder (RLE).
Read the Verilog module in the editor. The catalog line for this block: An 8-bit Run-Length Decoder that repeats an input value for a specified count.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit data path width.
8-bit run count support.
Synchronous valid output signaling.
Asynchronous active-low reset.
Simple control interface.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Asynchronous reset, active low
valid_in	Input	1	Input data valid signal
count	Input	[7:0]	Number of times to repeat the value
value	Input	[7:0]	Data value to be repeated
valid_out	Output	1	Output data valid signal
dout	Output	[7:0]	Decoded output data

Architecture

The design uses a down-counter to track remaining repetitions. When valid_in is asserted, the counter loads the count input. The output dout is driven by the value input. On subsequent cycles, the counter decrements until it reaches zero. The valid_out signal remains high while the counter is greater than zero.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Result
TC1	Basic Single Pulse (Count=1)	PASS
TC2	Multi-Cycle Run (Count=3)	PASS
TC3	Zero Count Handling	PASS
TC4	Reset During Run	PASS

All tests passed successfully. Simulation uses Icarus Verilog. VCD dump is available at sim/dump.vcd. Use the RtlStudio Waveform tab to view signals.

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