Coding & Line Codes
Hamming (7,4) Decoder
A synchronous Hamming (7,4) error-correcting decoder that detects and corrects single-bit errors in a 7-bit codeword, outputting the corrected 4-bit data.
About this block
Simulate it in the Verilog IDE
Hamming (7,4) Decoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP core implements a synchronous Hamming (7,4) Error-Correcting Code (ECC) decoder.
It accepts a 7-bit codeword and outputs the corrected 4-bit data payload.
The module is designed for high-speed integration, supporting a valid/ready-like handshake protocol via valid_in and valid_out signals.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Hamming (7,4) Decoder.
- Read the Verilog module in the editor. The catalog line for this block: A synchronous Hamming (7,4) error-correcting decoder that detects and corrects single-bit errors in a 7-bit codeword, outputting the corrected 4-bit data.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Single-Bit Error Correction: Automatically corrects any single-bit error in the 7-bit input codeword.
- Error Detection: Asserts
error_flaghigh when a single-bit error is detected and corrected. - Pipeline Friendly: Uses synchronous
valid_in/valid_outhandshaking to integrate easily into data pipelines. - Compliance: Written in Verilog-2001; synthesizable by all major EDA tools.
- Verified: Includes a comprehensive testbench covering all 8 possible single-bit error positions plus the no-error case.
Architecture
The decoder operates in two main stages:
- Syndrome Calculation: A 3-bit syndrome is computed using XOR operations over specific bit positions of the input codeword. The syndrome value corresponds directly to the 1-based index of the erroneous bit.
- Correction and Extraction: If the syndrome is non-zero, the corresponding bit is flipped. The 4 data bits are then extracted from the corrected codeword and registered on the positive clock edge.
### Data Mapping
The Hamming (7,4) code maps 4 data bits (D1-D4) and 3 parity bits (P1-P3) into 7 codeword bits. The decoder extracts the data bits from their specific positions in the corrected codeword.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | System clock input |
rst_n | Input | 1 | Active-low asynchronous reset |
codeword_in | Input | 7 | Received Hamming codeword (bits 0-6) |
valid_in | Input | 1 | Assert high when codeword_in is valid |
data_out | Output | 4 | Corrected 4-bit data payload |
error_flag | Output | 1 | High if a single-bit error was detected/corrected |
valid_out | Output | 1 | High when data_out and error_flag are valid |
Verification
The included testbench (tb_hamming_7_4_decoder.v) verifies the design against all possible single-bit error scenarios. It checks that the correct data is recovered and that the error_flag is asserted appropriately.
### Test Cases
| Test Case | Input Error Position | Expected data_out | Expected error_flag | Status |
|---|---|---|---|---|
| TC1 | No Error | Correct Data | 0 | PASS |
| TC2 | Bit 0 (P1) | Correct Data | 1 | PASS |
| TC3 | Bit 1 (P2) | Correct Data | 1 | PASS |
| TC4 | Bit 2 (D1) | Correct Data | 1 | PASS |
| TC5 | Bit 3 (P3) | Correct Data | 1 | PASS |
| TC6 | Bit 4 (D2) | Correct Data | 1 | PASS |
| TC7 | Bit 5 (D3) | Correct Data | 1 | PASS |
| TC8 | Bit 6 (D4) | Correct Data | 1 | PASS |
*Note: Specific data values depend on the input codeword. The table above indicates logical correctness.*
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