Coding & Line Codes

4-Bit Hex to 7-Segment Display Decoder

Combinational logic module that decodes 4-bit hexadecimal inputs into 7-segment display signals with configurable active-high or active-low polarity.

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4-Bit Hex to 7-Segment Display Decoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP implements a combinational decoder that maps 4-bit hexadecimal inputs to 7-segment display outputs. It supports both active-high and active-low segment driving configurations via a control pin. The design covers all hexadecimal digits 0 through F, plus a blank state for undefined inputs.

This module provides a robust and simple interface for driving 7-segment displays. It handles both common-anode and common-cathode display types via the active_low pin. The design is fully combinational with no internal state or clock dependencies. It is suitable for educational projects and simple display interfaces.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Hex to 7-Segment Display Decoder.
Read the Verilog module in the editor. The catalog line for this block: Combinational logic module that decodes 4-bit hexadecimal inputs into 7-segment display signals with configurable active-high or active-low polarity.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The core logic uses a case statement to map each 4-bit input value to its corresponding 7-segment pattern. The internal register dout_reg holds the active-high segment values. An assign statement conditionally inverts the output based on the active_low control signal. This approach ensures minimal latency and deterministic combinational behavior.

Ports

Port Name	Direction	Width	Description
`din`	Input	[3:0]	4-bit hexadecimal input data
`dout`	Output	[6:0]	7-segment output (a-g)
`active_low`	Input	1	Polarity control (0=Active High, 1=Active Low)

Verification

The testbench verifies functionality for all 16 hexadecimal states in both active-high and active-low modes. It iterates through inputs 0x0 to 0xF and checks the output against expected bit patterns. A watchdog timer ensures the simulation terminates if an infinite loop occurs. All 32 test cases (16 for each polarity) passed successfully.

Test Case	Description	Result
TC1	Active High Verification (0-F)	PASS
TC2	Active Low Verification (0-F)	PASS

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