Coding & Line Codes

NRZ-to-NRZI Line Encoder — L2 Upgrade

Pipelined NRZ-to-NRZI line encoder with backpressure support.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

NRZ-to-NRZI Line Encoder — L2 Upgrade is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a pipelined NRZ-to-NRZI line encoder. It converts Non-Return-to-Zero (NRZ) data into Non-Return-to-Zero Inverted (NRZI) format, suitable for physical layer interface designs.

This IP provides a simple, low-latency NRZ-to-NRZI encoder.

It features a single pipeline stage for minimal delay and supports backpressure via the out_ready signal (currently implemented as a constant high for simplicity).

Choose Open in IDE. RTL Studio loads the packaged workspace for NRZ-to-NRZI Line Encoder — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Pipelined NRZ-to-NRZI line encoder with backpressure support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The encoder consists of input registers and a stateful output register. Input data is latched on the rising clock edge when in_valid is asserted. Combinational logic determines the next output state based on the latched input. The output register updates the NRZI state on the clock edge.

NRZI Encoding Rules:

Logical '1' input: Toggles the signal level.
Logical '0' input: Maintains the current signal level.

Key Features:

Latency: 1-cycle latency between input validity and output validity.
Backpressure: Supports flow control via out_ready (currently hardcoded to 1 for simplicity).
Reset: Asynchronous active-low reset initializes all internal states to 0.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`in_valid`	Input	1	Input data valid signal
`in_data`	Input	1	Input NRZ data bit
`out_ready`	Output	1	Output ready signal (Hardcoded to 1)
`out_valid`	Output	1	Output data valid signal
`out_data`	Output	1	Output NRZI data bit

Verification

The testbench verifies the following behaviors:

Reset Behavior: Outputs are zero after reset.
Encoding Logic: Toggles on consecutive '1' inputs.
State Holding: Maintains state on '0' inputs.
Backpressure: Confirms out_ready is always high.
Invalid Input: Ensures state does not change when in_valid is low.

All test cases pass in the simulation log.

More in Coding & Line Codes

All Coding & Line Codes blocks