Coding & Line Codes

Bit Unstuffer After 5 Ones — L2 Upgrade

Bit unstuffer with stream enable and lock detect for serial data integrity.

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About this block

Simulate it in the Verilog IDE

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Bit Unstuffer After 5 Ones — L2 Upgrade is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a serial bit unstuffer with stream gating, lock detection, and error detection capabilities.

It monitors an input data stream to ensure synchronization integrity by detecting consecutive ones.

The module asserts a lock signal upon detecting five consecutive ones and an err signal upon detecting six consecutive ones (a stuffing violation).

Lock Detection: Asserts the lock output signal when five consecutive 1 bits are detected on the input stream.
Error Detection: Asserts the err output signal when six consecutive 1 bits are detected, indicating a violation of the bit-stuffing rule.
Stream Gating: The data_out is valid only when stream_en is high and err is low. Otherwise, data_out is forced to 0.
Reset Behavior: All internal states (counter, lock, error) are reset to zero when rst_n is low or stream_en is disabled.

Choose Open in IDE. RTL Studio loads the packaged workspace for Bit Unstuffer After 5 Ones — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Bit unstuffer with stream enable and lock detect for serial data integrity.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Synchronous design with active-low reset.
Configurable lock threshold (5 consecutive ones).
Configurable error threshold (6 consecutive ones).
Stream enable control for power management or data flow control.
Zero output on error or when stream is disabled.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`stream_en`	Input	1	Stream enable signal
`data_in`	Input	1	Input data bit
`data_out`	Output	1	Output data bit
`lock`	Output	1	Lock detected signal (asserted on 5 consecutive ones)
`err`	Output	1	Error detected signal (asserted on 6 consecutive ones)

Verification

The provided testbench (tb_bit_unstuff.v) verifies the following scenarios:

Reset Check: Ensures all outputs are zero after reset.
Idle State: Verifies behavior when stream_en is low.
Data Passthrough: Checks that data is passed through correctly when no lock/error conditions exist.
Lock Detection: Confirms lock is asserted after five consecutive ones.
Error Detection: Confirms err is asserted after six consecutive ones.
Stream Enable Recovery: Verifies state recovery when stream_en toggles.

To run the simulation, use your preferred HDL simulator (e.g., ModelSim, VCS, Xcelium) with the provided testbench.

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