Coding & Line Codes

4b/6b Run-Length Limited Encoder

A 4b/6b Run-Length Limited encoder and decoder with disparity control for DC balance.

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About this block

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4b/6b Run-Length Limited Encoder is a SystemVerilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

An OpenIP implementation of a 4b/6b Run-Length Limited (RLL) encoder and decoder. This IP ensures DC balance and limits consecutive identical bits in serial data streams. The design is suitable for high-speed serial communication links.

This IP provides a robust 4b/6b RLL coding solution for serial communication links. It features a simple architecture using pre-initialized lookup tables for encoding and decoding. Sequential running disparity state tracking ensures DC balance. The IP includes a comprehensive testbench for verification.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4b/6b Run-Length Limited Encoder.
Read the SystemVerilog module in the editor. The catalog line for this block: A 4b/6b Run-Length Limited encoder and decoder with disparity control for DC balance.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Bidirectional Data Flow: Supports separate host and decoder interfaces with valid/ready handshaking.
DC Balance: Maintains running disparity state to ensure zero DC component.
Error Detection: Decoder flags invalid codewords via dec_err.
High Performance: Uses combinational logic with LUTs for fast encoding/decoding.
Verification: Includes a built-in testbench with passing test cases.

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low reset
`host_valid`	Input	1	Host input data valid
`host_ready`	Output	1	Host input data ready
`host_data`	Input	4	Host input data
`enc_out`	Output	6	Encoded output data
`enc_valid`	Output	1	Encoded output valid
`enc_ready`	Input	1	Encoder output ready
`dec_valid`	Input	1	Decoder input valid
`dec_ready`	Output	1	Decoder input ready
`dec_in`	Input	6	Decoder input data
`dec_out`	Output	4	Decoded output data

Architecture

The module consists of an encoder block and a decoder block.

Encoder: Selects codewords based on current running disparity using lookup tables.
Decoder: Maps valid 6-bit codewords back to 4-bit data.
Disparity State: A sequential state machine tracks the running disparity to ensure DC balance.

Verification

The testbench verifies encoding and decoding functions. It checks specific codeword mappings for correctness. It validates error detection for invalid codewords.

### Expected Results

After running the simulation, the Log panel should show:

TC1 PASS
TC2 PASS
TC3 PASS
TC4 PASS
TC5 PASS
Simulation ends with INFO: PASS.

### Test Cases

Test Case	Description	Result
TC1	Encode input 0	PASS
TC2	Encode input 1	PASS
TC3	Decode valid RD-1 code	PASS
TC4	Decode invalid code	PASS
TC5	Decode valid RD+1 code	PASS

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