Golay (24,12) Encoder with Syndrome Calculator

Features

• Streaming Interface: Valid/ready handshake protocol.
• Configurable Pipeline: Supports 0, 1, or 2 pipeline stages via the PIPELINE_DEPTH parameter.
• Parity Inversion: Optional bitwise inversion of parity bits via the INVERT_PARITY parameter.
• Syndrome Output: Computes a 12-bit syndrome for immediate error detection.
• Synthesizable: Latch-free RTL compatible with major synthesis tools (Vivado, Quartus, etc.).

Interface

The module uses a simple valid/ready handshake protocol.

Note on ready_in: This signal is an output from the encoder indicating it is ready to accept data. It is hardwired to 1'b1, meaning the encoder never stalls the upstream producer. The upstream producer should drive valid_in based on its own data availability.

Signal Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
valid_in	Input	1	Valid input data flag
ready_in	Output	1	Ready for input (Always 1)
data_in	Input	12	12-bit data payload
valid_out	Output	1	Valid output codeword flag
ready_out	Input	1	Ready to accept output from downstream
codeword_out	Output	24	24-bit encoded codeword
syndrome_out	Output	12	12-bit syndrome/parity bits

Parameters

Parameter	Default	Description
PIPELINE_DEPTH	1	Number of pipeline stages (0, 1, or 2).

Higher depth improves Fmax but adds latency. |

Architecture

The encoder generates parity bits using XOR logic derived from the Golay generator matrix. The codeword is formed by concatenating the original 12-bit data and the 12-bit syndrome bits.

1. Combinational Logic: Computes the 12-bit syndrome from the 12-bit input data.
2. Codeword Formation: Concatenates data_in and syndrome (optionally inverted).
3. Pipeline Register: Registers the codeword and valid signal based on the PIPELINE_DEPTH setting.

Verification

The included testbench validates the following scenarios:

• TC1: Generation of 1024 random codewords and structural verification.
• TC2: Uniqueness of syndromes for single-bit errors.
• TC3: Minimum Hamming distance verification via syndrome checks.

All test cases pass successfully.

Integration

• Timing: Ensure timing constraints are set for the chosen PIPELINE_DEPTH.

Typical Fmax ranges from 200MHz (0 stages) to 400MHz+ (2 stages) depending on target technology.

• Reset: The module uses an active-low asynchronous reset (rst_n).
• Backpressure: Since ready_in is always 1, the encoder will always accept input when valid_in is high.

Ensure upstream logic handles backpressure if the producer cannot sustain the rate.

• Throughput: Ensure downstream logic can handle the throughput or implement backpressure on valid_in if necessary.