Coding & Line Codes

HDLC Bit Stuffing (5 Ones)

Inserts a zero bit after five consecutive one bits in a serial data stream for HDLC framing.

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HDLC Bit Stuffing (5 Ones) is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

An IP core implementing the HDLC bit stuffing mechanism. It inserts a '0' after five consecutive '1' bits in the data stream to ensure the flag pattern (01111110) does not appear in the payload.

This IP provides a standard, resource-efficient HDLC bit stuffing function suitable for framing layers in serial communication protocols.

It supports synchronous operation with a single clock domain using a valid/ready handshake for flow control.

Choose Open in IDE. RTL Studio loads the packaged workspace for HDLC Bit Stuffing (5 Ones).
Read the Verilog module in the editor. The catalog line for this block: Inserts a zero bit after five consecutive one bits in a serial data stream for HDLC framing.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Standard Compliance: Implements HDLC bit stuffing (insert '0' after five consecutive '1's).
Flow Control: Uses AXI-like valid/ready handshake for synchronous operation.
Resource Efficient: Minimal logic usage with a 3-bit counter and simple state machine.
Synchronous Design: Single clock domain with active-low synchronous reset.
Backpressure: Asserts ready_o low during the stuffing cycle to block input.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock signal
rst_n	Input	1	Active-low reset
valid_i	Input	1	Input data valid
ready_o	Output	1	Input ready (low during stuffing)
data_i	Input	1	Input data bit
valid_o	Output	1	Output data valid
data_o	Output	1	Output data bit

Architecture

The module maintains a 3-bit counter for consecutive ones. It operates in two main states: normal passing and stuffing.

Normal Mode: Passes input data directly to the output. The counter increments on input '1' and resets on input '0'.
Stuffing Mode: When the counter reaches four (indicating five consecutive ones including the current input), the next cycle enters stuffing mode. The module outputs a '0', resets the counter, and asserts ready_o low to block further input until the stuffed bit is processed.

Verification

The testbench verifies basic data passing and stuffing logic. It checks that zeros are inserted after five consecutive ones, that the counter resets on non-one bits, and that input is blocked during the stuffing cycle.

Test Case	Description	Expected Result
TC1	No Stuffing (000)	Data passes through unchanged
TC2	Single One	Data passes through unchanged
TC3	Four Ones	Data passes through unchanged
TC4	Five Ones	Stuffed zero inserted after fifth one
TC5	Six Ones	Stuffed zero after fifth, sixth passes

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