Coding & Line Codes

HDLC Bit-Stuff Remover

Removes stuffed zero bits from an HDLC serial data stream after five consecutive ones.

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About this block

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Mediumverilogsimsyn

HDLC Bit-Stuff Remover is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an HDLC bit-stuff remover. It removes stuffed zero bits inserted after five consecutive ones, adhering to the standard HDLC framing rule (IEEE 802.2 / ISO 13239).

The module processes a serial data stream using a synchronous finite state machine (FSM). It supports synchronous reset and a valid/ready handshake protocol for flow control. The design is optimized for low resource usage and has been verified with Icarus Verilog simulation.

Choose Open in IDE. RTL Studio loads the packaged workspace for HDLC Bit-Stuff Remover.
Read the Verilog module in the editor. The catalog line for this block: Removes stuffed zero bits from an HDLC serial data stream after five consecutive ones.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

HDLC Compliance: Removes stuffed zeros following five consecutive ones.
Data Integrity: Passes all other bits unchanged.
Flow Control: Supports synchronous valid/ready handshake via valid_in and valid_out.
Efficiency: Low resource usage with a simple 6-state FSM.
Verification: Verified with Icarus Verilog simulation against standard and edge cases.

Interface

Port Name	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Active-low synchronous reset
valid_in	input	1	Input data valid signal
data_in	input	1	Input data bit
valid_out	output	1	Output data valid signal
data_out	output	1	Output data bit

Architecture

The design uses a finite state machine to count consecutive ones. The states track the number of ones from zero to five. A transition to state five indicates five consecutive ones have been received. The next zero input is identified as a stuffed bit and is dropped by asserting valid_out low. All other bits are passed through with valid_out high.

### State Diagram

### Logic Explanation

States 0-4: Increment on data_in == 1, reset to State 0 on data_in == 0. Output data is passed through.
State 5 (5 consecutive ones):

- If data_in == 1: This is the 6th one. Reset count to 1 (State 1) and pass the bit. - If data_in == 0: This is the stuffed bit. Stay in State 5 (or effectively wait for next bit) and drop the bit by asserting valid_out low.

No Valid Input: If valid_in is low, the state holds, and outputs are suppressed.

Verification

The testbench verifies standard and edge cases. All tests passed successfully.

Test Case	Description	Result
TC1	Simple non-stuffed stream	PASS
TC2	Stuffed stream `0111110`	PASS
TC3	Encoder output for 6 ones	PASS
TC4	Reset behavior	PASS

### Running Simulation

To verify the design:

Ensure Icarus Verilog (iverilog) and GTKWave are installed.
Run the simulation script:
Check the log output for INFO: PASS.

### Expected Results

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