About this block
Simulate it in the Verilog IDE
Hamming (7,4) Encoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This OpenIP implements a Hamming (7,4) error-correcting code encoder in Verilog. The module takes 4-bit data inputs and generates 7-bit codewords with 3 parity bits. The layout matches the companion Hamming (7,4) Decoder for consistent indexing.
This IP provides a standard Hamming (7,4) encoder for error correction. It is suitable for digital communication and storage systems. The design is simple, combinational, and fully verified.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Hamming (7,4) Encoder.
- Read the Verilog module in the editor. The catalog line for this block: Hamming (7,4) Encoder.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Generates single-error-correcting Hamming (7,4) codewords.
- Uses XOR gates for parity calculation.
- Supports 4-bit parallel data input.
- Outputs 7-bit codeword with parity bits at positions 1, 2, and 4.
- Includes a comprehensive testbench with 16 input combinations.
- Verified with Icarus Verilog simulation.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| data_in | Input | [3:0] | 4-bit data input |
| codeword | Output | [6:0] | 7-bit encoded codeword |
Architecture
The encoder calculates three parity bits based on specific data bit combinations. Parity bit P1 covers bits 1, 2, and 4 of the data. Parity bit P2 covers bits 1, 3, and 4 of the data. Parity bit P4 covers bits 2, 3, and 4 of the data. The final codeword is assembled with parity bits at positions 0, 1, and 3 (0-indexed).
Verification
The testbench iterates through all 16 possible 4-bit input values. Each input is compared against the expected Hamming codeword. Spot checks verify zero vector, ones vector, and specific patterns. All 16 tests passed successfully in simulation. No errors were detected during verification.
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