Coding & Line Codes

8-Bit Nibble-Swap Endian Converter — L1 Upgrade — L2 Upgrade

8-bit nibble-swap endian converter with registered outputs, stream enable, and lock detect for identical nibbles.

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About this block

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8-Bit Nibble-Swap Endian Converter — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a registered 8-bit nibble-swap endian converter. It swaps the upper and lower nibbles of an 8-bit input data stream. This module is suitable for data path manipulation in streaming applications where byte-endian conversion is not required, but nibble-level reordering is necessary.

This IP core provides a simple, registered 8-bit nibble-swap function with stream control and lock detection capabilities.

It is designed for integration into streaming data paths where nibble-level reordering is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Nibble-Swap Endian Converter — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit nibble-swap endian converter with registered outputs, stream enable, and lock detect for identical nibbles.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Nibble Swap: Swaps bits [7:4] with [3:0].
Registered Output: Data and control signals are registered for improved timing closure.
Stream Enable: Supports conditional updating of outputs via stream_en.
Lock Detect: Identifies when the input upper and lower nibbles are identical.
Active-Low Reset: Synchronous reset logic.

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`stream_en`	Input	1	Stream enable control. High to update outputs.
`data_in`	Input	8	Input data to be swapped
`lock_detect_en`	Input	1	Enable lock detection logic
`valid_out`	Output	1	High when `stream_en` is high and data is valid
`data_out`	Output	8	Swapped output data
`lock_detected`	Output	1	High if input nibbles are identical

Architecture

The design consists of a combinatorial nibble-swap logic followed by a registered output stage. The registered stage is gated by stream_en.

Verification

The provided testbench (tb_nibble_swap_endian_enable_registered_stream_enable_lock.v) verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Basic Nibble Swap (0xAB)	`data_out` = 0xBA, `valid_out` = 1
TC2	Reverse Nibble Swap (0x12)	`data_out` = 0x21
TC3	Lock Detect Match (0x11)	`lock_detected` = 1
TC4	Lock Detect Mismatch (0x12)	`lock_detected` = 0
TC5	Stream Enable Disable	`valid_out` = 0
TC6	Reset Behavior	All outputs = 0

### Running Simulation

Open your preferred Verilog simulator (e.g., ModelSim, VCS, Xcelium).
Compile the RTL and testbench files.
Run the simulation.
Check the log for INFO: PASS.

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