Coding & Line Codes

8-Bit Manchester Encoder (IEEE 802.3 Compliant)

An 8-bit parallel-to-serial Manchester encoder with Ready/Valid handshake and backpressure support.

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About this block

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8-Bit Manchester Encoder (IEEE 802.3 Compliant) is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit parallel-to-serial Manchester encoder compliant with IEEE 802.3 standards. It converts 8-bit parallel data into a serial Manchester-encoded stream with self-clocking properties. The design supports Ready/Valid handshaking for seamless integration into AXI-Stream or similar interfaces. Backpressure is handled via the host_ready signal to prevent data loss during busy periods.

This IP provides a robust and verified Manchester encoder for 8-bit data. It integrates easily into systems requiring self-clocking serial communication. The Ready/Valid interface ensures reliable data transfer with backpressure support. Use the RtlStudio Waveform tab with sim/dump.vcd for detailed signal analysis.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Manchester Encoder (IEEE 802.3 Compliant).
Read the Verilog module in the editor. The catalog line for this block: An 8-bit parallel-to-serial Manchester encoder with Ready/Valid handshake and backpressure support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Encodes 8-bit parallel input into serial Manchester format.
Manchester encoding rule: bit 0 becomes 10, bit 1 becomes 01.
Supports Ready/Valid handshake protocol for flow control.
Implements backpressure logic to stall input when the encoder is busy.
Configurable clock divider for baud rate generation.
Resettable state machine with synchronous reset logic.
Verified against standard test patterns including 0x00, 0xFF, 0x55, and 0xAA.

Ports

Port Name	Direction	Width	Description
clk	Input	1	System clock input.
rst_n	Input	1	Active-low asynchronous reset.
host_valid	Input	1	Input data valid signal from host.
host_ready	Output	1	Output ready signal to host for backpressure.
host_data	Input	8	Parallel 8-bit data input.
serial_out	Output	1	Serial Manchester-encoded output bit.
serial_valid	Output	1	Output valid signal indicating valid serial data.

Architecture

The following diagram illustrates the internal data flow and control logic.

The clock divider generates a bit_period_pulse to synchronize the serial output rate. The control logic manages the busy state to enforce backpressure via host_ready. Data is shifted out bit-by-bit from MSB to LSB during the busy state. Each bit is encoded according to the Manchester rule before being asserted on serial_out.

Verification

The testbench validates the encoder against multiple scenarios to ensure correctness. Reset behavior is verified to ensure all outputs are deasserted and ready state is active. Single byte transmissions for 0x00, 0xFF, 0x55, and 0xAA are tested for encoding accuracy. Backpressure is verified by attempting to send data while the encoder is busy. The simulation log confirms all test cases pass without errors.

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Data 0x00	PASS
TC3	Data 0xFF	PASS
TC4	Data 0x55	PASS
TC5	Data 0xAA	PASS
TC6	Backpressure	PASS
TC7	Data 0x5A	PASS

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