Coding & Line Codes

8b/10b Encoder and Decoder

A dual-mode 8b/10b encoder and decoder with running disparity support and control character handling.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

8b/10b Encoder and Decoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a high-performance, dual-mode 8b/10b encoder and decoder compliant with IEEE 802.3 and ANSI X3.230 standards. It ensures DC balance through robust running disparity management and supports all standard data characters (D.0-D.31) and control characters (K.x), including the special K28.5 synchronization character.

Designed for seamless integration into high-speed serial links (PCIe, SATA, Ethernet PHYs), the module features a standard AXI-Stream-like ready/valid handshake interface for efficient flow control and back-pressure handling. This module is ideal for physical layer implementations requiring low latency, error detection, and reliable line coding.

This IP core provides a robust, standards-compliant 8b/10b encoding and decoding solution suitable for high-speed serial communication interfaces. It offers dual-mode operation, comprehensive error detection, and a standard ready/valid interface for easy integration into existing FPGA designs. The core ensures DC balance and low latency, making it ideal for PCIe, SATA, and Ethernet PHY implementations. Users can integrate the core using the provided instantiation example and verify functionality using the included testbench results.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8b/10b Encoder and Decoder.
Read the Verilog module in the editor. The catalog line for this block: A dual-mode 8b/10b encoder and decoder with running disparity support and control character handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Dual-Mode Operation: Simultaneous independent encoding and decoding paths.
Standard Compliance: Full support for D.0-D.31 and K.28.5 control characters.
DC Balance: Internal running disparity tracking ensures zero DC component on the serial link.
Error Detection: Flags invalid code groups and disparity errors in the decoder path.
Ready/Valid Interface: Standard handshake protocol for back-pressure and flow control.
Low Latency: Combinational logic for mapping with registered outputs for timing closure.
Configurable: Optional start signal support for burst transfers.

Architecture

The top-level module (ecc_8b10b) instantiates two independent sub-modules:

Encoder: Converts 8-bit input data into 10-bit code groups using ROM-based lookup tables and running disparity logic.
Decoder: Converts 10-bit code groups back into 8-bit data, validating code groups and checking disparity consistency.

The design uses finite state machines (FSMs) for control logic and ROM-based lookup tables for character mapping. Running disparity is tracked internally and exposed via output signals (enc_disp, dec_disp) for cascading or monitoring purposes.

Verification

The IP has been verified using a comprehensive testbench covering:

Reset behavior
Standard data character encoding/decoding (D.0, D.31, D.5, D.26)
Control character handling (K28.5)
Running disparity transitions (positive/negative)
Error handling for invalid codes
Round-trip integrity (encode then decode)
Continuous stream and random data patterns

All test cases passed successfully.

Test Case	Description	Result
TC1	Reset state check	PASS
TC2	Encode D.0 (0x00)	PASS
TC3	Encode D.31 (0xFF)	PASS
TC4	Encode K28.5	PASS
TC5	Disparity check for D.0	PASS
TC6	Disparity check for D.31	PASS
TC7	Disparity check for K28.5	PASS
TC8	Decode D.0	PASS
TC9	Decode D.31	PASS
TC10	Decode K28.5	PASS
TC11	Decoder disparity check	PASS
TC12	Decoder error handling	PASS

More in Coding & Line Codes

All Coding & Line Codes blocks