8-Bit Differential Encoder/Decoder (NRZ-D) — L1 Upgrade — L2 Upgrade

Features

• 8-bit Parallel Data Path: Supports 8-bit input and output data buses.
• NRZ-D Encoding: Implements data_out = data_in ^ prev_out for differential encoding.
• Registered Pipeline: Includes a registered pipeline stage to register input and previous output, improving timing performance.
• Stream Enable Control: Supports a stream_en signal to pause processing without losing internal state.
• Lock Detect Mechanism: Asserts a flag after detecting 8 consecutive zero-byte inputs, useful for idle detection.
• Synchronous Reset: All internal registers are reset synchronously via rst_n.
• Valid Signal Propagation: Handles valid_in and valid_out signals with enable gating.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low synchronous reset
stream_en	Input	1	Stream enable control signal
data_in	Input	[7:0]	Input data bus
valid_in	Input	1	Input valid signal
data_out	Output	[7:0]	Encoded/decoded data bus
valid_out	Output	1	Output valid signal
lock_detect	Output	1	Lock detect flag (high after 8 zeros)

Architecture

The module uses a single pipeline stage to register the input data and the previous output value. This ensures that the XOR operation uses stable registered values.

1. Pipeline Stage: The input data and previous output are registered. The XOR operation computes the new output based on these registered values.
2. Lock Detect Logic: A counter tracks consecutive zero bytes in the input stream. When the count reaches 8, the lock_detect output is asserted. Any non-zero byte resets the counter to zero.
3. Stream Enable: The stream_en signal gates the processing of valid_in. When stream_en is low, the output valid is deasserted, and the internal state (including prev_out_reg and zero_count) is held.

Integration

To integrate this IP into your design:

1. Instantiate the module differential_encoder_registered_pipelined_8bit_stream_enable_lock.
2. Connect your system clock to clk and active-low reset to rst_n.
3. Drive data_in and valid_in with your source data.
4. Control flow with stream_en.
5. Monitor lock_detect for idle stream detection.

Verification

The testbench verifies reset behavior, basic encoding, stream enable control, and lock detect logic. All test cases passed successfully in the simulation log.

Test Case	Description	Result
TC1	Reset State	PASS
TC2	Basic Encoding (NRZ-D)	PASS
TC3	Stream Enable Control	PASS
TC4	Lock Detect - 8 consecutive zeros	PASS
TC5	Lock Detect Reset on non-zero	PASS
TC6	Lock Detect - 8 consecutive zeros again	PASS