Coding & Line Codes

NRZI to NRZ Decoder

Converts NRZI encoded signals to standard NRZ format by detecting transitions.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

NRZI to NRZ Decoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a lightweight, synchronous NRZI (Non-Return-to-Zero Inverted) to NRZ decoder.

It converts NRZI encoded signals into standard NRZ format by toggling the output on input transitions.

The design is optimized for area efficiency, requiring only a single flip-flop for state retention, making it ideal for high-speed serial interfaces and area-constrained FPGA designs.

Logic High (1) on nrzi_in: Indicates a transition (toggle).
Logic Low (0) on nrzi_in: Indicates no transition (hold).

Choose Open in IDE. RTL Studio loads the packaged workspace for NRZI to NRZ Decoder.
Read the Verilog module in the editor. The catalog line for this block: Converts NRZI encoded signals to standard NRZ format by detecting transitions.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design utilizes a single synchronous flip-flop to store the previous input state (prev_nrzi). The output logic is defined as:

$$ nrz_{out}[n] = nrz_{out}[n-1] \oplus nrzi_{in}[n] $$

This means the output toggles when nrzi_in is high and holds its value when nrzi_in is low.

Interface

Signal	Direction	Width	Description
`clk`	Input	1	System clock input
`rst_n`	Input	1	Active-low asynchronous reset
`nrzi_in`	Input	1	NRZI encoded data input
`nrz_out`	Output	1	Decoded NRZ data output

Verification

The provided testbench (tb_nrzi_to_nrz_decoder) validates the following scenarios:

Test Case	Description	Expected Result
TC1	Reset Check	Output is `0` after reset
TC2	Known Sequence	Correct decoding of `1, 0, 1, 0, 1`
TC3	All Zeros	Output holds previous state
TC4	All Ones	Output toggles every cycle

### Running Simulation

Compile the RTL and testbench.
Run the simulation.
Check the log for PASS messages corresponding to each test case.

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