Coding & Line Codes

Reed-Solomon (8b) Encoder

A Reed-Solomon encoder for 8-bit symbols using GF(2^8) arithmetic with generator polynomial x^2 + 0x03*x + 0x02.

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About this block

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Reed-Solomon (8b) Encoder is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP provides a low-latency, synchronous Reed-Solomon encoder for 8-bit symbols over GF(2^8).

It generates two parity bytes (16 bits) per input symbol using a shift-and-XOR engine.

The design is optimized for high-speed data paths, ensuring parity output is available shortly after input assertion.

Choose Open in IDE. RTL Studio loads the packaged workspace for Reed-Solomon (8b) Encoder.
Read the Verilog module in the editor. The catalog line for this block: A Reed-Solomon encoder for 8-bit symbols using GF(2^8) arithmetic with generator polynomial x^2 + 0x03*x + 0x02.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Systematic Encoding: Computes parity for 8-bit symbols.
Synchronous Design: Uses a clocked interface for reliable integration into synchronous pipelines.
Standard GF(2^8): Uses primitive polynomial $x^8 + x^4 + x^3 + x^2 + 1$ (0x11D).
Self-Checking Testbench: Includes a Verilog testbench with automatic pass/fail reporting.

Architecture

The encoder maintains two 8-bit remainder registers (r1, r0). It processes the 8-bit data_in bit-by-bit (MSB first) within a single clock cycle using a shift-and-XOR engine. The logic is pipelined such that the output is valid on the rising edge of the clock following the assertion of valid.

### Logic Flow

Reset: When rst_n is low, r1 and r0 are initialized to 0.
Encoding: When valid is high, the 8-bit data_in is processed over 8 clock cycles (or internally within the cycle depending on implementation depth).
Feedback: For each bit, registers are shifted. If the MSB of r1 is 1, it XORs with pre-computed feedback constants derived from the generator polynomial coefficients (0x03 and 0x02).
Output: The concatenated remainders {r1, r0} are driven to p_out on the clock edge.

Verification

The included testbench performs self-checking verification for the following cases:

Test Case	Input (`data_in`)	Expected Parity (`p_out`)	Description
TC1	0x00	0x0000	Reset/Idle state check.
TC2	0xFF	0x8408	All-ones input check.
TC3	0x01	0x8000	Single bit set check.
TC4	0xAB	0x780c	Random pattern check.

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