Coding & Line Codes

Reversible 8b/10b Encoder (No-Data-Loss, Low-Power)

Implements 8b/10b encoding with DC balance and run-length constraints using deterministic lookup tables.

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About this block

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Reversible 8b/10b Encoder (No-Data-Loss, Low-Power) is a SystemVerilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This OpenIP implements an 8b/10b encoder with running-disparity tracking for DC balance. It maps 8-bit data symbols to 10-bit codes using standard 5b/6b and 3b/4b tables. The RTL is combinational with a registered disparity state and is verified in SystemVerilog with Verilator.

Choose Open in IDE. RTL Studio loads the packaged workspace for Reversible 8b/10b Encoder (No-Data-Loss, Low-Power).
Read the SystemVerilog module in the editor. The catalog line for this block: Implements 8b/10b encoding with DC balance and run-length constraints using deterministic lookup tables.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Deterministic encoding for all 256 data codes (D-codes).
Running disparity (disp_state) updated each cycle.
Registered code_out for clean timing closure.
K-code coverage in the testbench for control-character checks.
Synthesis-friendly SystemVerilog without latches in the verified build.

Ports

Port	Direction	Width	Description
`clk`	input	1	System clock
`rst_n`	input	1	Active-low reset
`data_in`	input	8	Input byte
`valid`	input	1	Input valid
`code_out`	output	10	Encoded symbol
`code_out_k`	output	1	K-character flag
`ready`	output	1	Always ready (registered path)

Integration

Reset disp_state using rst_n before link bring-up. Pair this encoder with a matching 8b/10b decoder on the receive path. Verify link partners agree on K/D code usage.

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