Coding & Line Codes

Scramble LFSR Stream 8-bit

An 8-bit scrambler using a Galois LFSR with polynomial x^8 + x^6 + x^5 + x^4 + 1. It XORs input data with the LFSR state for data randomization.

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About this block

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Scramble LFSR Stream 8-bit is a Verilog reference block in the Coding & Line Codes catalog. Line codes, serializers, and digital encoding/decoding blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit Galois Linear Feedback Shift Register (LFSR) scrambler.

It is designed to randomize data streams for applications such as communication link testing, memory testing, or clock data recovery (CDR) training.

The design supports synchronous data handshaking via valid_in/valid_out signals and initializes to a known seed (0xAB) upon reset, ensuring reproducible simulation results.

Choose Open in IDE. RTL Studio loads the packaged workspace for Scramble LFSR Stream 8-bit.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit scrambler using a Galois LFSR with polynomial x^8 + x^6 + x^5 + x^4 + 1. It XORs input data with the LFSR state for data randomization.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Parallel Interface: Processes 8 bits of data per clock cycle.
Galois LFSR Configuration: Efficient hardware implementation using the polynomial $x^8 + x^6 + x^5 + x^4 + 1$ (Hex: 0x91).
Handshaking Protocol: Uses valid_in and valid_out signals to manage data flow and backpressure.
Deterministic Reset: Synchronous reset initializes the LFSR state to 0xAB.
State Hold: The LFSR state is preserved when valid_in is low, preventing unintended state transitions during idle periods.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low asynchronous reset
`data_in`	Input	8	Input data to be scrambled
`valid_in`	Input	1	Input data valid indicator
`data_out`	Output	8	Scrambled output data
`valid_out`	Output	1	Output data valid indicator

Architecture

The module consists of two main stages:

Scrambling Stage: When valid_in is asserted, the input data data_in is XORed with the current LFSR state to produce data_out.
LFSR Update Stage: On every clock cycle where valid_in is high, the LFSR state is updated according to the Galois polynomial taps. If valid_in is low, the LFSR state remains unchanged.

### Galois Polynomial Implementation

The polynomial $x^8 + x^6 + x^5 + x^4 + 1$ corresponds to the tap positions at bits 7, 6, 5, and 4 (using 0-indexed LSB). The feedback logic updates the register as follows:

Bit 0 takes the value of Bit 1.
Bit 1 takes the value of Bit 2.
Bit 2 takes the value of Bit 7 (Feedback).
Bit 3 takes the value of Bit 4.
Bit 4 takes the value of Bit 5 XOR Bit 7.
Bit 5 takes the value of Bit 6 XOR Bit 7.
Bit 6 takes the value of Bit 7 XOR Bit 7 (which is 0, effectively shifting in 0 if not for the specific Galois structure, but here it's a shift register).

*Note: The specific Verilog implementation uses a parallel update logic to ensure correct timing.*

Verification

The testbench verifies reset behavior, LFSR progression, and valid data propagation. All six test cases passed successfully in the simulation log.

Test Case	Description	Result
TC1	Reset state XOR check	PASS
TC2	LFSR step 1 check	PASS
TC3	LFSR step 2 check	PASS
TC4	LFSR step 3 check	PASS
TC5	Valid propagation with non-zero data	PASS
TC6	Invalid input does not change output	PASS

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