Control & Timers

Activity Timeout Flag 8-bit — L2 Upgrade

Captures 8-bit activity signals and generates a sticky IRQ and timeout flag when masked inactivity exceeds a configurable cycle count.

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About this block

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Activity Timeout Flag 8-bit — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core detects inactivity on an 8-bit data bus.

It monitors masked activity signals and asserts a sticky interrupt request (IRQ) and a timeout flag if no activity is detected for a configurable number of clock cycles.

The module supports synchronous enable, asynchronous reset, and synchronous clear for robust system integration.

Choose Open in IDE. RTL Studio loads the packaged workspace for Activity Timeout Flag 8-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Captures 8-bit activity signals and generates a sticky IRQ and timeout flag when masked inactivity exceeds a configurable cycle count.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Activity Monitoring: Captures activity signals with bitwise masking capabilities.
Configurable Timeout: 16-bit counter allows precise configuration of the inactivity threshold.
Sticky IRQ: Generates a persistent interrupt request that must be explicitly cleared.
Reset & Clear: Supports asynchronous active-low reset (rst_n) and synchronous active-high clear (clear).
Power Gating: Synchronous enable (en) control for power management.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Synchronous enable
`clear`	Input	1	Active-high synchronous clear
`activity_mask`	Input	8	Bitwise mask for activity input
`activity_in`	Input	8	Activity signal input
`timeout_cycles`	Input	16	Counter threshold for timeout
`irq`	Output	1	Sticky interrupt request
`active_flags`	Output	8	Masked activity status
`timeout_flag`	Output	1	Timeout detection flag

Verification

The testbench verifies six key scenarios to ensure correct functionality:

Test Case	Description	Result
TC1	Basic Activity Tracking	PASS
TC2	No Activity Counter Increment	PASS
TC3	Sticky IRQ Capture	PASS
TC4	Clear Functionality	PASS
TC5	Activity Resets Counter	PASS
TC6	Masking Logic	PASS

All tests passed successfully with zero errors.

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