Control & Timers

8-Bit Window Comparator — L1 Upgrade — L2 Upgrade

8-Bit Window Comparator with sticky IRQ capture and synchronous clear.

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8-Bit Window Comparator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit window comparator that monitors a data stream against configurable lower and upper bounds. It provides two primary outputs:

in_window: A combinational signal indicating if the input data is currently within the specified range.
irq_sticky: A sequential, sticky interrupt signal that asserts high upon the first transition of data_in into the window. It remains asserted until explicitly cleared via irq_clear or a system reset (rst_n).

This design is suitable for applications requiring detection of transient events within a specific data range, ensuring that entry events are captured even if the data leaves the window immediately.

The module operates synchronously with a clock (clk) and an active-low asynchronous reset (rst_n).

Window Check: Combinational logic compares data_in against lower_bound and upper_bound.
Sticky IRQ Logic: Sequential logic detects the rising edge of the window condition (transition from outside to inside) and latches the interrupt state.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Window Comparator — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit Window Comparator with sticky IRQ capture and synchronous clear.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Data Width: Supports 8-bit input data and bounds.
Configurable Bounds: Independent lower_bound and upper_bound inputs.
Sticky Interrupt: irq_sticky asserts on window entry and holds state.
Synchronous Clear: irq_clear resets the sticky interrupt without affecting the window check logic.
Asynchronous Reset: rst_n resets all internal state immediately.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`data_in`	Input	[7:0]	Data to compare
`lower_bound`	Input	[7:0]	Lower bound of window
`upper_bound`	Input	[7:0]	Upper bound of window
`irq_clear`	Input	1	Synchronous IRQ clear
`in_window`	Output	1	High if `lower_bound <= data_in <= upper_bound`
`irq_sticky`	Output	1	Sticky IRQ triggered on window entry

Architecture

The design separates combinational comparison from sequential state management to ensure deterministic behavior.

Combinational Stage: in_window_comb is calculated every cycle based on input bounds.
Edge Detection: A D-Flip-Flop (prev_in_window) stores the previous cycle's window status. An edge detector identifies the transition from 0 to 1.
Sticky Latch: The sticky register (irq_sticky_q) is set on the detected edge and cleared by irq_clear or rst_n.

Verification

The provided testbench (tb_window_comparator_sticky_8_sticky_irq_capture.v) validates the following scenarios:

Test Case	Description	Expected Result
TC1	Data inside window	`in_window` is 1
TC2	Data below window	`in_window` is 0
TC3	Transition into window	`irq_sticky` becomes 1
TC4	Data stays inside	`irq_sticky` remains 1
TC5	Data leaves window	`irq_sticky` remains 1
TC6	IRQ clear asserted	`irq_sticky` becomes 0
TC7	Reset asserted	`irq_sticky` becomes 0
TC8	Re-trigger after clear	`irq_sticky` becomes 1 again

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